AR# 32505

描述

When I cross-probe into FPGA Editor from Timing Analyzer, I receive several warnings and the cross-probing does not work. The warnings look similar to the following:

"WARNING:InterToolCommunication:23 - The Xilinx TCL command interpreter communicating with a Xilinx tool returned the following: "error writing "sock2972": connection reset by peer" "XilItc::Send {XilItc::Highlight clearall -all -sender {Timing Analyzer}}""

"WARNING:InterToolCommunication:23 - The Xilinx TCL command interpreter communicating with a Xilinx tool returned the following: "error writing "sock2972": connection reset by peer" "XilItc::Send {XilItc::Collection -begin; XilItc::Highlight highlight -bel {COUNTNUM_0} -sender {};XilItc::Highlight highlight -net {COUNTNUM_0} -sender {};XilItc::Highlight highlight -bel {Mcount_COUNTNUM_xor<3>1} -sender {};XilItc::Highlight highlight -bel {COUNTNUM_3} -sender {};XilItc::Collection -end }""

解决方案

This issue seems to occur when FPGA Editor is launched from Timing Analyzer, closed, and launched again.

To prevent this from occurring, perform all cross-probing in a single session of FPGA Editor.

To work around this issue, save all current timing analysis, close Timing Analyzer, re-open Timing Analyzer, and launch FPGA Editor again by clicking on Launch FPGA Editor. Cross-probing should work correctly until FPGA Editor is closed.

This issue is scheduled to be fixed in the next major release of the software.