AR# 32521

11.1 Virtex-5 MAP Known Issues - Incorrect optimization of latch with Gate driven by constant "1" but GE driven by active signal

描述

I have a latch in my design with G constantly high and an active signal on D. It has been optimized away so as to pass through the D signal despite the fact that GE is active. Is this optimization problem a known issue?

解决方案

This latch optimization issue is scheduled to be fixed in ISE 11.2.

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AR# 32521
日期	05/23/2014
状态	Archive
Type	综合文章
器件	Virtex-5 FXT Virtex-5 LX Virtex-5 LXT More Virtex-5 SXT Virtex-5 TXT Virtex-5Q Virtex-5QV Less
Tools	ISE Design Suite - 11.1

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