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AR# 32531

12.4/13.4/14.7 Virtex-5 Place - Known Issue where Clock Placer does not handle placement of BUFR driving BUFG properly


My design is unconstrained, but is failing during placement due to the following error describing a non-optimal placement of the clock components.

The BUFGCTRL component mentioned has one input driven by a BUFR.  
Why is the placer not able to find an optimal clock placement since one is available? 

ERROR:Place:592 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock 
IOB / BUFGCTRL site pair. The clock IOB component <FPGA_CLK> is placed at site <H14>. The corresponding BUFG 
component <U3_BUFG> is placed at site <BUFGCTRL_X0Y10> The clock IO site can use the fast path between the IO and the 
Clock buffer if the IOB & BUFGCTRL are both placed in the same half of the device (TOP or BOTTOM). You may want to 
analyze why this problem exists and correct it. If this sub optimal condition is acceptable for this design, you may 
use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design 
to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It 
is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock 
placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. 


The placement of the global clocks and regional clocks in a design are performed by separate algorithms that take into account the specific rules associated with each clock type.  
The global clock placer is responsible for ensuring that the BUFG and GCLKIOB are placed in an optimal location.  
The regional clock placer is responsible for ensuring that all BUFR loads are placed in a clock region that can be accessed by the BUFR.  
These two algorithms are not designed to work in concert to handle a circuit that combines both global and regional buffers.

There are no plans to fix this issue since it is considered to be a low frequency issue.

If a circuit constrains both BUFR and BUFG clock buffers, they will need to be locked into an optimal placement configuration, unless the non-optimal GCLKIOB placement is acceptable.
AR# 32531
日期 09/11/2014
状态 Active
Type 综合文章
  • Virtex-5
  • Virtex-5Q
  • Virtex-5QV
  • ISE Design Suite - 14
  • ISE Design Suite - 13
  • ISE Design Suite - 12