AR# 32534: 11.1 Virtex-5 Route - Known Issue where the router creates route-thru conflict
11.1 Virtex-5 Route - Known Issue where the router creates route-thru conflict
My design appears to route successfully, but when DRC was run during BitGen, the following error occurs:
"ERROR:PhysDesignRules:796 - Component Scheduler/AdvancedScheduler/SlowCountersTop/Gen_SlowCounters.10.SlowCounters/ CHANNEL_2<0> has routethru conflicts."
What causes this error and how can I avoid it?
One reason this error can occur is that the router ignores loadless signals; therefore, it will not take them into account when checking the validity of a route-thru connection.
In ISE version 11.2, the router will correctly evaluate route-thrus and take loadless signals into account.
In the meantime, examine the routed design (NCD) in FPGA Editor and check to see if the component involved contains loadless signals. This can be performed by zooming in on the affected component, and then using the List Window to select all unrouted (because they are loadless) nets. Look for any highlighting on the affected component in the form of a red circle on an output pin. If no such highlighting is found, then the route-thru conflict is occurring for other reasons. If a loadless signal is found on the affected component, the problem can be resolved by either removing the loadless signal from the design, or by ensuring that the signal is loaded.