Xilinx has determined that the Clock Correction feature of the Virtex-5 GTX transceiver can cause data corruption on the Receiver when a clock correction sequence is skipped or added. The XAUI core is effected by this issue because it must use a clock correction sequence length of 1 byte to adhere to the IEEE 802.3 standard.
To work around this issue, it is possible to either use synchronous clocking or a fabric clock correction module. A full description of this issue and work-around is available in (Xilinx Answer 32164).
| AR# 32539 | |
|---|---|
| 日期 | 12/15/2012 |
| 状态 | Archive |
| Type | 综合文章 |