AR# 32543


11.1 Timing - Incorrect Clock Analysis after Inverting My Clock with a BUFIO2 or an INV


Timing analysis is being performed on an incorrect clock edge. My design usesan INV or a BUFIO2 to perform the clock inversion.How can I correct the analysis?


When using logic such as a LUT (INV) or even a BUFIO2 to invert a clock, the timing engine has no indication that the clock was inverted. The inverting components are viewed as combinatorial logic, not clock-modifying blocks.

To correct this issue, use local inversion or a clock-modifying block to invert the clock.DCM, DLL, PLL, BUFR, PMCD, and MMCM components are considered to be clock-modifying blocks.

AR# 32543
日期 02/05/2013
状态 Active
Type 综合文章
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