AR# 32599

11.1 Timing - Operating within specification of FIFO, but receiving component switching limit errors

描述

Keywords: pin, RAM, Virtex-6

I am receiving component switching limit errors on a FIFO, but I am operating within specifications. The Virtex-6 data sheet states:

Fmax_fifo FIFO in all modes -2 500 MHz

However, there are component switching limit violations like the ones below, in my timing report:

Component Switching Limit Checks: TS_Inst_mmcm1_clkout0 = PERIOD TIMEGRP "Inst_mmcm1_clkout0" TS_CLK HIGH
50%;
--------------------------------------------------------------------------------
Slack: -0.122ns (period - min period limit)
Period: 1.818ns
Min period limit: 1.940ns (515.464MHz) (Trper_CLKB)
Physical resource: Inst_fifo
Logical resource: Inst_fifo
Location pin: RAMB36_X1Y9.CLKBWRCLKL
Clock network: CLK
--------------------------------------------------------------------------------

解决方案

This issue is scheduled to be fixed in the next quarterly release.



AR# 32599
日期 06/05/2009
状态 Archive
Type 综合文章