AR# 32622

描述

I upgrade my FFT design to the latest version, but the later version needs more clock cycles to get output.

What is the reason for this discrepancy?

Is it possible for me to improve it?

解决方案

Since version 4.0 of the FFT Core, there was more pipelining due to the introduction of the DSP48s than the previously used MULT18x18. Therefore, there has been a change in the latency. If this is an issue, then it might be necessary to try a different architecture and/or change the parameters.