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AR# 32631

11.1 Timing - Why is my PLL Jitter lower than my System Jitter?

Description

When I look at my timing report, the DCM Jitter calculations correctly use my System Jitter. However, when I look at my PLLs, the PLL Jitter is less than the System Jitter.

Is this possible, or is there a problem with my timing report?

解决方案

By design, the PLLs can reduce jitter. This reduction in jitter is reflected in timing reports. Therefore, it is possible to see PLL Jitter at values lower than System Jitter.

AR# 32631
创建日期 06/05/2009
Last Updated 12/15/2012
状态 Active
Type 综合文章