PLB_PCI_v1_01_a fails in a livelock mode with a sequence of transactions as follows:
A remote PLB master is trying to read from the pci bus, but the request is retried by the remote PCI target; then, a remote PCI initiator makes a request from a PLB slave, but the PLB master has the PLB tied up so it cannot get on the PLB bus.
The timing of the PLB master request being transferred to the PCI side is such that the "abort" (due to the PLB read request tying up the PLB bus) is 1 clock off to stop the PCI read request to the PLB IPIF mst, and so the bridge gets in a confused state.
You can download the latest patch from:
- Please copy the "PLB_PCI_v1_01_a" from the EDK build 'pcores' repository to your project local "pcores".
- Unzip and replace the vhdl-files in the your local "pcores" directory (that is, under 'PLB_PCI_v1_01_a\hdl\vhdl')
with these latest files.
This core will be removed from EDK 12.1, and It will not be fixed.