AR# 32736: 11.1 EDK, MPMCv5.00.a - What is the depth of the MPMC NPI SRL FIFOs?
11.1 EDK, MPMCv5.00.a - What is the depth of the MPMC NPI SRL FIFOs?
Keywords: depth, size, corrupt, loss
What is the depth of the MPMC NPI SRL FIFOs? The data sheet is unclear on how to manage the SRL FIFOs.
The data sheet has been updated to add this information: Restrictions on SRL FIFOs
The user logic must prevent write FIFO overflows for NPI writes, facilitated by the use of the PIM<Port_Num>_WrFIFO_AlmostFull signal. MPMC does not prevent Read FIFO overflows when using the SRL FIFOs. The SRL FIFO can hold up to 64 words (64-bit NPI) or 32 words (32-bit NPI). Depending on the burst sizes being used, ensure that the total size of outstanding Read quests does not exceed the capacity of the SRL FIFO. For example, if 32-word bursts and 64-bit NPI are used, do not request more than two transactions with PIM<Port_Num>_AddrReq before reading out all 32 words of data from the first transaction.
This information has been added to the MPMC v5.02.a data sheet, to be released in EDK 11.2.