- Virtex-6 LXT, SXT, and CXT device support (NOTE: Virtex-6 solutions are pending hardware validation.) - Simplex design support for built-in timer
- Aurora does not initialize properly due to unstable clock during power-up (CR 473640) - Errors in synthesis for cores targeting the Virtex-5 TXT's right-hand GTX column (CR 521251)
- Virtex-6 FPGA solutions are pending hardware validation. - Oversampling support for both GTP and GTX devices has been removed. - Currently, the cores support up to 16 lanes. If more than 16-lane support is required, contact firstname.lastname@example.org - Timing errors for designs with transceivers selected at extreme end of columns. Refer to LogiCORE IP Aurora 8B10B v4.1 User Guide (UG353) for more details. - Manual edits required to use "orphaned" transceivers when Aurora uses only 1 transceiver in a DUAL (CR 503600). Refer to LogiCORE IP Aurora 8B10B v4.2 User Guide (UG353) for more details. - SCP and ECP do not support back-to-back frames (CR 505495). The Aurora Core requires that the SCP is transmitted in the most significant lane and that ECP is transmitted in the least significant lane. This reduces the bandwidth if the frames do not fit this scheme. - CORE Generator message regarding licensing is misleading: 'Full license for component <aurora_8b10b> allows you to use this component. This license does not give you access to source code implementing this component." The core does deliver HDL source code. - (Xilinx Answer 32695) Cannot directly replace Aurora transceiver tile wrapper with GTX Wizard's transceiver tile wrapper. - (Xilinx Answer 33284) Data alignment can be to either byte 0 or 2 for cores targeting GTX when using 4-byte interface - The last 2 bytes of a transmitted UFC message are corrupted when the UFC message size is greater than 14 bytes and there is a simultaneous clock correction sequence insertion. This applies only to one-lane, 2-byte designs with User Flow Control enabled.
Revision History 6/24/09 - Initial Release 8/14/09 - Added AR 33284