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AR# 3275

CPLD M1.3(patch),M1.4: Pin location assignments for 9500 designs are not seen

Description

Keywords: CPLD, pin, loc, abel, ucf, 9500

Urgency: Standard

General Description: Pin assignments may not seen by the CPLD fitter if:
1)pin assignments are made in the .ucf file.
2)pin assignments are made in abel design.
3)pin assignments are made in a schematic sheet other than the top level

解决方案

1

This problem was introduced by one of the M1.3 patches and
carried through to M1.4.

The current work around is to assign pin locations in a
guide(.gyd) file.

For using a guide file see (Xilinx Solution 2719).

For schematic designs, assign pin location on the top level schematic.

2

A patch is now available on the Xilinx Download area at:

http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/cpld_sol10_m14.tar.Z - for Solaris

http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/cpld_sun10_m14.tar.Z - For SunOS

http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/cpld_hp10_m14.tar.Z - For Hp-UX

http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/cpld_nt10_m14.zip - For Win'95/NT

These update files also include the changes from previous cpld updates.

All zip files are created using WinZip. To obtain this utility,
access WinZip's web site at http://www.winzip.com

3


The M1.4 patch does not resolve a known issue where macro I/O
cells are instantiated in the design (IPAD4, IBUF4) and the LOC
constraints are contained in a UCF file.

For this case, splitting the I/O into individual primitives
(IPAD, IBUF) is one alternative. The other is to use the GYD file.
AR# 3275
创建日期 01/09/1998
Last Updated 03/26/2000
状态 Archive
Type 综合文章