This answer record contains the Release Notes and Known Issues for the CORE Generator tools and LogiCORE IP Video Timing Controller.
The following information is listed for each version of the core:
Video Timing Controller Core Page:
https://www.xilinx.com/products/intellectual-property/ef-di-vid-timing.html
General LogiCORE IP Video Timing Controller Issues
| (Xilinx Answer 34828) | How do I simulate my Video IP pCore in EDK? |
| (Xilinx Answer 39413) | What signals are needed for the timing to be correctly detected and regenerated? |
| (Xilinx Answer 47158) | Why do I not see blanking signals generated when I select the blanking signal detection? |
LogiCORE IP Video Timing Controller v5.01.a
There is a v5.01.a Rev3 patch available in (Xilinx Answer 52846).
This patch was intended to fix issues listed below as (Xilinx Answer 52724), (Xilinx Answer 54610), (Xilinx Answer 54611) and (Xilinx Answer 55980).
Supported Devices (ISE)
Supported Devices (Vivado)
Bug Fixes
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
Known Issues (ISE)
| (Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
| (Xilinx Answer 52666) | Software Driver v3.00.a - Why did the software the software driver only ever see one instance of the Video Timing Controller when using SDK in 2013.3/14.3? |
| (Xilinx Answer 52724) | Why does the VTC Generation always wait for the VTC Detection to lock, when both the VTC Generation and VTC Detection are enabled? |
| (Xilinx Answer 52741) | Why is the VTC Generation always producing 720p output timing signals at startup when the AXI4-Lite interface is used? |
| (Xilinx Answer 54610) | Why do I get an NGD Build error when using the VTC v5.01.a in 14.3 IDS EDK? |
| (Xilinx Answer 54611) | Why does Video Timing Controller Generator reset early in relation to the Blanking Signals, if both the detector and the generator are enabled? |
| (Xilinx Answer 55980) | Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock? |
Known Issues (Vivado)
| (Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
| (Xilinx Answer 52666) | Software Driver v3.00.a - Why did the software the software driver only ever see one instance of the Video Timing Controller when using SDK in 2013.3/14.3? |
| (Xilinx Answer 52724) | Why does the VTC Generation always wait for the VTC Detection to lock, when both the VTC Generation and VTC Detection are enabled? |
| (Xilinx Answer 52741) | Why is the VTC Generation always producing 720p output timing signals at startup when the AXI4-Lite interface is used? |
| (Xilinx Answer 54611) | Why does Video Timing Controller Generator reset early in relation to the Blanking Signals, if both the detector and the generator are enabled? |
| (Xilinx Answer 55980) | Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock? |
LogiCORE IP Video Timing Controller v5.00.a
Supported Devices (ISE)
Supported Devices (Vivado)
New Features
Bug Fixes
| (Xilinx Answer 51847) | Why do I get an error about the component not being found, when trying to simulate the Video Timing Controller v4.00.a? |
Known Issues (ISE)
| (Xilinx Answer 52724) | Why does the VTC Generation always wait for the VTC Detection to lock, when both the VTC Generation and VTC Detection are enabled? |
Known Issues (Vivado)
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 52724) | Why does the VTC Generation always wait for the VTC Detection to lock, when both the VTC Generation and VTC Detection are enabled? |
LogiCORE IP Video Timing Controller v4.00.a
Supported Devices (ISE)
Supported Devices (Vivado)
New Features
Bug Fixes
Known Issues
| (Xilinx Answer 51249) | Software Driver v2.00.a - Why did the software driver stop working with my Video Timing Controller core after updating to the latest version of the ISE Design Suite? |
| (Xilinx Answer 51847) | Why do I get an error about the component not being found, when trying to simulate the Video Timing Controller v4.00.a? |
LogiCORE IP Video Timing Controller v3.0
New Features
Bug Fixes
Known Issues
| (Xilinx Answer 50241) | Why do I receive a BRESP error when trying to perform a soft reset using the command 0xA0000000 as recommended by the documentation? |
LogiCORE IP Video Timing Controller v2.1
Bug Fixes
Detection Status Registers readable in pCore Added "OPTION USAGE_LEVEL = BASE_USER" to pCore MPD file Resolved detection interrupt issues
| (Xilinx Answer 35436) | Why am I having problems reading the Interrupt Status Registers? |
| (Xilinx Answer 33829) | Why are the detection ports still in the VHO file, when I did not select them in the core generation GUI? |
| (Xilinx Answer 33830) | Why do I see a mismatch between the behavioral simulation and the post-implementation gate level simulation results, when using the default GUI Values for Max Clock Per Line and the Max Lines Per Frame? |
| (Xilinx Answer 35039) | Why is the captured value for the vertical timing incorrect, or why is the status register not being updated, when targeting Spartan-6 or Virtex-6 devices? |
| (Xilinx Answer 38729) | Why does the Video Timing Controller pCore fail to generate in EDK with an XST error? |
Known Issues
| (Xilinx Answer 38545) | Why is the Video Timing Controller so large when using the pCore interface? |
| (Xilinx Answer 38546) | Why are the number of lines per frame being incorrectly detected? |
LogiCORE IP Video Timing Controller v2.0
New Features
Bug Fixes
| (Xilinx Answer 32913) | Why do some Max Lines Per Frame values cause an "XST failed for v_timebase_v1_0" error during generation? |
Known Issues
| (Xilinx Answer 33829) | Why are the detection ports still in the VHO file, when I did not select them in the core generation GUI? |
| (Xilinx Answer 33830) | Why do I see a mismatch between the behavioral simulation and the post-implementation gate level simulation results, when using the default GUI Values for Max Clock Per Line and the Max Lines Per Frame? |
| (Xilinx Answer 35436) | Why am I having problems reading the Interrupt Status Registers? |
| (Xilinx Answer 35039) | Why is the captured value for the vertical timing incorrect, or why is the status register not being updated, when targeting Spartan-6 or Virtex-6 FPGA? |
| (Xilinx Answer 38729) | Why does the Video Timing Controller pCore fail to generate in EDK with an XST error? |
LogiCORE IP Video Timing Controller v1.0
New Features
Bug Fixes
Known Issues
| (Xilinx Answer 32913) | Why do some Max Lines Per Frame values cause a "XST failed for v_timebase_v1_0." error during generation? |
| AR# 32754 | |
|---|---|
| 日期 | 07/19/2018 |
| 状态 | Archive |
| Type | 版本说明 |
| IP |
|