Trce/Timing Analyzer are missing the worst-case timing paths through address pins of block RAM components in ISE design tools 10.x and older.
This change occurs in 11.2. This issue only affects block RAM elements. Timing paths were missing to the address pins of the block RAM. The timing analysis would analyze some, but not all the correct address pins of the block RAM. It would analyze an odd number of the address pins, but not all or the correct ones. Now, all the address pins are analyzed, regardless of the DATA_WIDTH setting. The Timing Analyzer tools analyze the address pins correctly if a signal is driving them. The timing report from the analysis in 11.2, or the patched version of 10.1.03/11.1, has an increase in the number of items or paths analyzed. This increase in the timing report is expected. Once 11.2 or the patch is installed, you will need to re-implement the design to insure you meet timing on these new timing paths.