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AR# 32769

FIFO Generator v5.2 - Release Notes and Known Issues for ISE 11.2


Keywords: CORE Generator, IP, update, fifogen, asynchronous, synchronous, common, clocks, memory, block RAM, BRAM, RAMB16, FIFO16, asynch, asymmetric, non-symmetric, first, word, fall, through, fwft

This Release Notes and Known Issues Answer Record is for the FIFO Generator v5.2 Core, released in ISE 11.2 and contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues
- Device Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:


General Information

(Xilinx Answer 22014) When using FIFO Generator Core, the allowed data count width is less than it should be
(Xilinx Answer 22722) FIFO Generator Core now includes a User Guide in addition to a data sheet. Where can I find the User Guide for the FIFO Generator?
(Xilinx Answer 24712) How do I test user logic that triggers ECC SBITERR and DBITERR outputs in FIFO Generator?
(Xilinx Answer 30029) Setup/Hold time violations occur in the Unconstrained Path Report
(Xilinx Answer 31144) Differences between FIFO v4.x (and newer) cores and v3.x (and prior) cores

New Features in v5.2

- ISE 11.2 support

- Virtex-6 and Spartan-6 device support

- (Xilinx Answer 32738) Enhanced the behavioral models to be cycle accurate for FULL, EMPTY, ALMOST_FULL, ALMOST_EMPTY, WRITE_DATA_COUNT, READ_DATA_COUNT, WR_ACK, VALID, UNDERFLOW and OVERFLOW

- (Xilinx Answer 32737) DOUT reset value support for block RAM based FIFO with embedded register

Bug Fixes in v5.2

(Xilinx Answer 31381) Empty flag does not assert in Common Clock (block RAM based) behavioral model simulation
- Version fixed: v5.2
- CR 471467 and 473003

- FIFO generator user guide has incorrect description for Non-Symmetric Aspect Ratios
- Version fixed: v5.2
- CR 518140

Known Issues in v5.2

- Virtex-6 and Spartan-6 solutions are pending hardware validation

- Software Support for the Virtex-6 Lower Power parts was added in this release, but FIFO Generator is not yet supported and cannot be generated from CORE Generator. In order to work around this issue, you can set your project to target an equivalent Virtex-6 LXT device which will allow you to generate a place holder IP that can be regenerated when support for the Virtex-6 Lower Power parts is added in 11.3.

(Xilinx Answer 24003) NC-Sim warning occurs when targeting Virtex-5
(Xilinx Answer 23691) Behavioral simulation models are not supported for built-in FIFO configuration
(Xilinx Answer 20291) During simulation X_FF RECOVERY and SETUP warnings occur
(Xilinx Answer 20271) Simulation error occurs on RESET
(Xilinx Answer 30226) When writing to an EMPTY FIFO, PROG_FULL might assert earlier than expected
(Xilinx Answer 31379) When importing an XCO file, user cannot change read/write clock frequencies with Built-in FIFO
(Xilinx Answer 32740) Write Data Count is not cycle accurate in behavioral model for non symmetric aspect ratios of 1:4 and 1:8 when FWFT is used
(Xilinx Answer 32739) Last word not read out of FIFO using Virtex-6 Built In FIFO
(Xilinx Answer 32988) Virtex-6 Built-In FIFOs targeting FIFO36E1 primitives fail to generate

Revision History
06/24/2009 - Initial Release
07/06/2009 - Added ARs 32739 and 32988 to Known Issues
AR# 32769
日期 07/06/2009
状态 Active
Type 综合文章