An erroneous instruction bus exception can occur when writing to TLB registers, if an instruction fetch coincides with the TLB register write instruction. The error can only occur when C_ICACHE_ALWAYS_USED is set, and the processor is running in virtual mode with the instruction cache enabled.
| AR# 32926 | |
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| 日期 | 05/21/2014 |
| 状态 | Archive |
| Type | 综合文章 |
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| IP | |