AR# 32929

Virtex-6 - 11.x Software Known Issues related to the Virtex-6 FPGA

描述

Are there any Virtex-6 FPGA related known issues with the 11.2, 11.3, 11.4, or 11.5 ISE Design Suite software release?

* Please note the Virtex-6 FPGA Production designs must use 12.1 or later ISE software. See (Xilinx Answer 35493) for Virtex-6 FPGA related software known issues for 12.x ISE Design Suite.

解决方案

11.5:

The following set of known issues require design changes and re-implementation of existing designs:
(Xilinx Answer 33849) Virtex-6 FPGA MMCM - New Requirements for all MMCMs, VCO minimum frequency, and CLKFBOUT_MULT_F values
(Xilinx Answer 34859) Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap

Chipscope Pro
(Xilinx Answer 33824) 11.4 ChipScope, IBERT GTH - "ERROR:sim - Error: ngdbuild failed on prime_top. ERROR:ConstraintSystem:58 "
(Xilinx Answer 34674) 11.x ChipScope - IBERT - Virtex-6 GTX: Coregen does not list upper GTXE1 quads of SX475T and LX550T
(Xilinx Answer 34683) 11.x ChipScope - Virtex-6 - IBERT parameter sweep tests show errors in the middle of the eye
(Xilinx Answer 34901) 11.5 ChipSocpe - IBERT - The following error has occurred. Error: map failed on chipscope_ibert. ERROR:PhysDesignRules:1997 - The computed value for the VCO operating frequency of MMCM_ADV instance

EDK
(Xilinx Answer 34564) 11.5 EDK - Clock_Generator v3.02.a, Virtex-6 MMCM CLKFBOUT_MULT_F = 2, 3, 4 not valid
(Xilinx Answer 34678) 11.5 EDK, XPS_LL_TEMAC - "ERROR:PhysDesignRules - Invalid configuration..."

Embedded Tri-mode Ethernet MAC
(Xilinx Answer 33195) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - Adjusting IDELAYs to meet GMII and RGMII setup and hold requirements
(Xilinx Answer 33362) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - "Warning:Par:468 - Your design did not meet timing" seen in some configurations

MAP
(Xilinx Answer 34693) 11.5 MAP - Patch available for LUTRAM trimming issue introduced by 11.5

MIG
(Xilinx Answer 34094) - MIG v3.3, Virtex-6 FPGA DDR2/DDR3 - MMCM CLKFBOUT_MULT_F= 4 not valid, manual modification required

MPMC
(Xilinx Answer 34099) MPMC v5.04.a - "ERROR:LIT:586 - MMCM_ADV symbol "mpmc_core_0/.../u_mmcm_clk_base" has attribute CLKFBOUT_MULT_F set to a value that is outside the valid range of 5 to 64."

PCI Express
(Xilinx Answer 33763) - Virtex-6 FPGA Integrated Block Wrapper v1.4, v1.4 rev 1, and v1.4 rev 2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.4 and 11.5
(Xilinx Answer 34611) - Virtex-6 FPGA Integrated Block Wrapper v1.4 rev 2 for PCI Express - Patch to Enable VHDL File Generation for v1.4 rev 2 released in ISE 11.5
(Xilinx Answer 34612) - Virtex-6 FPGA Integrated Endpoint Block v1.4 for PCI Express - Simulation failure when using ISE 11.5 to simulate a v1.4 core generated in ISE Design Suite 11.4

SPI-3
(Xilinx Answer 34264) SPI-3 Link Layer v7.1 Rev1 - Virtex-6 BRAM resource utilization in 11.5 data sheet is not accurate
(Xilinx Answer 33779) SPI-3 Link Layer v7.1 and v7.1 Rev1 - Release Notes and Known Issues for ISE 11.4 and 11.5 software

SPI 4.2
(Xilinx Answer 33313) SPI4.2 v9.3, v9.3 Rev1 and v9.3 Rev2 - Release Notes and Known Issues for ISE 11.3/11.4/11.5
(Xilinx Answer 34252) SPI-4.2 Lite v5.1 Rev2 - Virtex-6 Block RAM resource utilization in 11.5 data sheet is not accurate

10-Gigabit Ethernet MAC v9.3
(Xilinx Answer 34783) LogiCORE IP 10-Gigabit Ethernet MAC v9.3 - Virtex-6 FPGA block RAM parameterization might result in memory collisions during simulation and erroneous operation

Tri-Mode Ethernet MAC v4.3
(Xilinx Answer 34764) LogiCORE IP Tri-Mode Ethernet MAC v4.3 - Virtex-6 FPGA block RAM parameterization might result in memory collisions during simulation and erroneous operation



11.4:

The following set of known issues require design changes and re-implementation of existing designs:
(Xilinx Answer 34164) Virtex-6 11.4 ISE - Virtex-6 designs must be re-run through implementation in the next release of software
(Xilinx Answer 33849) Virtex-6 FPGA MMCM - New Requirements for all MMCMs, VCO minimum frequency, and CLKFBOUT_MULT_F values

* Some IP require updates to meet requirements for block RAM Read and Write collision avoidance in all Virtex-6 block RAM operating in Read First mode with Asynchronous Clocking. Check the list below to see which IP are affected.

ChipScope Pro
(Xilinx Answer 33701) 11.3 ChipScope IBERT - "ERROR:HDLCompiler:1318 - "<path>/xsdb_bus_controller.vhd" Line 416: Left bound value <15> of slice is out of range [7:0] of array <sl_sel_i>"
(Xilinx Answer 33524) 11.3 ChipScope Pro analyzer - IBERT - CORE Generator interface crashes when I hit generate for my Virtex-6/Spartan-6 FPGA IBERT core
(Xilinx Answer 33920) 11.x ChipScope Pro tool - IBERT - Virtex-6 FPGA - Clock Pattern on Reflck is incorrect

Clocking Wizard
(Xilinx Answer 33938) 11.4 Clocking Wizard - Virtex-6 MMCM dynamic phase shift not configured correctly

Constraints Editor
(Xilinx Answer 32483) 11.1 Known Issue - Constraints Editor - Why does my Net Period constraint show "NA" for my clock?

CORE Generator
(Xilinx Answer 33728) 11.3 Licensing - Free, licensed IP cores fail to generate or implement - No license for component <IP coren name> found
(Xilinx Answer 33933) 11.4 CORE Generator - Generating an iBERT IP core results in "wincg.exe has encountered a problem and needs to close" error message

CORE Generator Block Memory Generator
(Xilinx Answer 33322) Block Memory Generator v3.3 - Why do I see setup violations when I simulate my Virtex-6 device SDP memory?
(Xilinx Answer 34259) Block Memory Generator v3.3 - Block RAM collision requirements not met

CORE Generator FIFO Generator
(Xilinx Answer 33395) FIFO Generator v5.3 - DOUT reset value does not function correctly on a Virtex-6 device Built In FIFO

CORE Generator MIG
(Xilinx Answer 33832) MIG v3.3, Virtex-6 FPGA DDR3 DIMM - MIG does not allocate two sets of CK/CK#, CS and ODT for data widths that two DIMMs
(Xilinx Answer 33807) MIG v3.3, Virtex-6 FPGA, DDR2/DDR3 - The VHDL traffic generator hangs after a few reads for designs with a Burst Length of 4
(Xilinx Answer 33831) MIG v3.3, Virtex-6 QDRII+ FPGA - Warning Messages are displayed in the Bank Selection terminal/console

CORE Generator MIG DDR2 SDRAM
(Xilinx Answer 33804) MIG v3.3, Virtex-6 FPGA, DDR2 - Timing parameter tRC min is violated if CAS Latency (CL) equals 4 with 2T timing
(Xilinx Answer 33803) MIG v3.3, Virtex-6 FPGA, DDR2/DDR3 - Read Modify Write command fails when using Data Mask to mask individual bytes

CORE Generator MIG DDR3 SDRAM
(Xilinx Answer 33441) MIG v3.2, v3.3, Virtex-6 FPGA DDR2/DDR3 - The periodic reads associated with the phase detector are not properly sent according to the tPRDI timing parameter
(Xilinx Answer 33418) MIG v3.2, v3.3, Virtex-6 FPGA DDR3 - When I target a RDIMM with CWL=7, the design does not drive the correct write data in OTF mode

CORE Generator PCI Express
(Xilinx Answer 33834) Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Use of Component Name "core" Causes Implementation Failures using VHDL Flow
(Xilinx Answer 32934) Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - 250 MHz Reference Clock Required for GEN 2 Mode of Operation
(Xilinx Answer 33837) Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - x8 GEN2 Operation is not supported in Virtex-6 HXT devices for the v1.4 release
(Xilinx Answer 33835) Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Area Group Constraints to Assist in x8 GEN 2 Timing Closure
(Xilinx Answer 33836) Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Cannot Generate x8 GEN 2 Core for LX130T device using -2 speedgrade
(Xilinx Answer 34033) Virtex-6 Integrated Block Wrapper for PCI Express - The v1.4 core might fail to train reliably in Engineering Sample silicon

CORE Generator POS PHY Lite
(Xilinx Answer 32920) SPI-4.2 Lite v5.1 - Virtex-6 design might fail timing in PAR

CORE Generator RapidIO
(Xilinx Answer 33453) Serial RapidIO v5.4 - VHDL example design simulation error with core_clk.vhd

CORE Generator Ten Gigabit Ethernet RXAUI
(Xilinx Answer 33486) LogiCORE XAUI v9.1 and RXAUI v1.1 - Update needed for reset logic in block level for Spartan-6 Device GTP and Virtex-6 Device GTX wrappers
(Xilinx Answer 33488) LogiCORE XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX powerdown reset logic should be updated

MAP
(Xilinx Answer 33743) 11.3 Virtex-6 FPGA MAP - Change in trimming behavior related to IBUFDS_GTXE1 components
(Xilinx Answer 33340) 11.2 MAP/PAR - What is meant by Multi-Threading support in ISE 11.2?
(Xilinx Answer 33576) Virtex-6 MMCM, 11.3 MAP - MMCM does not lock and "Error:PhysDesignRules:2045" for PFD frequencies above 300 MHz with Bandwidth set LOW

PAR
(Xilinx Answer 33021) 11.2 Virtex-6 Place - Designs with very low utilization may have very poor QOR
(Xilinx Answer 33377) MIG v3.2, v3.3, Virtex-6 FPGA RLDRAMII - Design is unroutable when Debug Signals are turned on

PlanAhead
(Xilinx Answer 33189) 11.2 PlanAhead - Bank color incorrect in the device and package view

RocketIO Virtex-6 GTX Wizard
(Xilinx Answer 33454) Serial RapidIO v5.4 - Virtex-6 FPGA hardware validation updates

SPI-3 Link Layer
(Xilinx Answer 33809) SPI-3 Link Layer v7.1 - Virtex-6 FPGA core timing simulation reports memory collision errors in block RAM
(Xilinx Answer 34157) SPI-3 v7.1 - Virtex-6 core should not be used in production due to potential block RAM memory collision

SPI-4.2
(Xilinx Answer 34155) SPI4.2 v9.3 - Virtex-6 core should not be used in production due to potential block RAM memory collision
(Xilinx Answer 34156) SPI4.2 Lite v5.1 - Virtex-6 core should not be used in production due to potential block RAM memory collision

System Generator
(Xilinx Answer 33877) 11.4 System Generator for DSP - "ERROR:HDLCompiler:377 - Entity port sl_addrack does not match with type std_logic of component port sl_addrack is declared here"

Timing and Constraints
(Xilinx Answer 33927) 11.4 MAP - ERROR:Place:864 - Incompatible IOB's are locked to the same bank 0


11.3:

General
(Xilinx Answer 32959) Virtex-6, Spartan-6 - When will the Virtex-6 or Spartan-6 electrical simulation models be published?
(Xilinx Answer 33515) Known Issues for Virtex-6 HXT devices

ChipScope Pro
(Xilinx Answer 33242) 11.2, 11.3 ChipScope Pro Analyzer IBERT - Moving the sampling point slider sets EYE_SCAN_MODE attribute auto to manual

Constraints Editor
(Xilinx Answer 32483) 11.1 Known Issue - Constraints Editor - Why does my Net Period constraint show "NA" for my clock

CORE Generator Block Memory Generator
(Xilinx Answer 33322) Block Memory Generator v3.3 - Why do I see setup violations when I simulate my Virtex-6 device SDP memory?

CORE Generator FIFO Generator
(Xilinx Answer 33395) FIFO Generator v5.3 - DOUT reset value does not function correctly on a Virtex-6 device Built In FIFO

CORE Generator MIG
(Xilinx Answer 33403) MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - Simulation warnings are generated for mismatches in port connection sizes
(Xilinx Answer 33415) MIG v3.2, Virtex-6 FPGA DDR2DDR3 - Master Bank selection is not enabled in some cases which require a Master Bank
(Xilinx Answer 33389) MIG v3.2, Virtex-6 FPGA DDR3 - ODT values incorrectly set for component-based design
(Xilinx Answer 33405) MIG v3.2 Virtex-6 FPGA DDR2/DDR3 - When data mask is disabled, BitGen will fail with PhysDesignRules errors
(Xilinx Answer 33440) MIG v3.2, Virtex-6 FPGA DDR2 - When ODT is disabled (RTT_NOM = 0), ODT is incorrectly asserted immediately following calibration
(Xilinx Answer 33420) MIG v3.2, Virtex-6 FPGA DDR2 - No support for CL=6 with RDIMM devices
(Xilinx Answer 33409) MIG v3.2, Virtex-6 FPGA DDR2 and DDR3 - Traffic Generator (example_design) does not support DDR2 BL=4 and DDR2/DDR3 Data Widths greater then 72-bits
(Xilinx Answer 33443) MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - Read associated with Read Modified Write command is incorrectly issued as a Read with Auto-Precharge
(Xilinx Answer 33439) MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - ECC not supported for data widths equal to 120-bit
(Xilinx Answer 33441) MIG v3.2, Virtex-6 DDR2/DDR3 - The periodic reads associated with the phase detector are not properly sent according to the tPRDI timing parameter
(Xilinx Answer 33418) MIG v3.2, Virtex-6 FPGA DDR3 - When targeting a RDIMM with CWL=7, the design does not drive the correct write data in OTF mode
(Xilinx Answer 33419) MIG v3.2, Virtex-6 FPGA DDR3: No support available for CWL=8 for RDIMM devices
(Xilinx Answer 33413) MIG v3.2, Virtex-6 FPGA QDRII+ SRAM - The output example_top.ucf is missing the system clock period constraint and includes an incorrect BUFR constraint
(Xilinx Answer 33375) MIG v3.2, Virtex-6 FPGA RLDRAMII - Valid configurations to avoid tRC violations for -18, -25, -25E, and -33 devices
(Xilinx Answer 33402) MIG v3.2, Virtex-6 FPGA RLDRAMII - Data Mask signals are not properly propagated through the write path - RTL CHANGES REQUIRED
(Xilinx Answer 33376) MIG v3.2, Virtex-6 FPGA RLDRAMI - MAX tCK violations occur in simulation for -18 parts running at 370 MHz

CORE Generator POS PHY Lite
(Xilinx Answer 32920) PI-4.2 Lite v5.1 - Virtex-6 design might fail timing in PAR

CORE Generator Ten Gig Ethernet XAUI and RXAUI
(Xilinx Answer 33486) LogiCORE XAUI v9.1 and RXAUI v1.1 - Update needed for reset logic in block level for Spartan-6 Device GTP and Virtex-6 Device GTX wrappers
(Xilinx Answer 33488) LogiCORE XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX powerdown reset logic should be updated

CORE Generator PCI Express
(Xilinx Answer 32932) Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - VHDL example design and test bench not available
(Xilinx Answer 32915) Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - Use of the trn_rnp_ok_n signal not supported for the 8-lane Gen 2 Integrated Block Mode
(Xilinx Answer 32934) Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - 250 MHz Reference Clock Required for GEN 2 Mode of Operation
(Xilinx Answer 33127) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - UCF constraint for sys_clk incorrect for ML605
(Xilinx Answer 33106) Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - ModelSim simulation does not show all signals in hierarchy

MAP
(Xilinx Answer 33340) 11.2 MAP/PAR - What is meant by Multi-Threading support in ISE 11.2?

PAR
(Xilinx Answer 32922) SPI-4.2 Lite v5.1 - Virtex-6 design returns "ERROR:Place:418 - Failed to execute IOB Placement" in MAP
(Xilinx Answer 33021) 11.2 Virtex-6 Place - Designs with very low utilization may have very poor QOR
(Xilinx Answer 33362) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - "Warning:Par:468 - Your design did not meet timing" seen in some configurations
(Xilinx Answer 33377) MIG v3.2, Virtex-6 FPGA RLDRAMII - Design is unroutable when Debug Signals are turned on
(Xilinx Answer 33517) 11.3 Virtex-6 Place - Crash during placement phase 1.1 when GTX component is LOC'd, but corresponding IBUFDS is not
(Xilinx Answer 33576) Virtex-6 MMCM, 11.3 MAP - MMCM does not lock and "Error:PhysDesignRules:2045" for PFD frequencies above 300 MHz with Bandwidth set LOW

Timing and Constraints
(Xilinx Answer 33363) Virtex-6 Embedded Tri-mode Ethernet MAC Wrapper v1.3 - With 16-bit client interface, the wrong clock is used to analyze some client-side Ethernet MAC signals


11.2:

General
(Xilinx Answer 32862) Known Issues for Lower Power Virtex-6 -1L devices (limited IP and 3rd-party synthesis support)
(Xilinx Answer 32959) Virtex-6, Spartan-6 - When will the Virtex-6 or Spartan-6 electrical simulation models be published?
(Xilinx Answer 33126) Virtex-6 Block RAM - Why don't the maximum frequency limitations listed in the data sheet match what the software allows?
(Xilinx Answer 33124) Spartan-6 and Virtex-6 - General ES Patch for customers using ISE 11.2 Design Suite

ChipScope
(Xilinx Answer 32783) 11.2 ChipScope Pro - IBERT - ERROR:sim - Error: map failed on chipscope_ibert. ERROR:Pack:1107
(Xilinx Answer 32910) 11.2 ChipScope Pro - IBERT - ERROR - Device 1 Unit 1000

Constraints Editor
(Xilinx Answer 32837) 11.1 Constraints Editor - Clock port is listed as input pad for OFFSET IN constraints
(Xilinx Answer 32835) 11.2 Constraints Editor - Period Constraint value is not updated after Validate Constraint

PAR
(Xilinx Answer 32822) 11.2 Virtex-6 MAP - "ERROR:Place:1164 - The clock source component ... "

iMPACT
(Xilinx Answer 32724) 11.2 iMPACT - iMPACT crashes when I attempt to program a compressed non-encrypted bitstream after programming AES E-Fuse Registers
(Xilinx Answer 32781) 11.2 iMPACT - Efuse programming is disabled on Linux
(Xilinx Answer 32827) 11.2 iMPACT - Virtex-6 Indirect BPI Programming support

Simulation Libraries
(Xilinx Answer 32916) SPI-4.2 v9.2 - Virtex-6 Verilog timing simulation does not work with SDFMAX

GTP Wizard
(Xilinx Answer 32996) Virtex-5/Virtex-6 GTP/GTX and Spartan-6 GTP Transceiver Wizard - Timing not met on implemented example design

CORE Generator MIG
(Xilinx Answer 32872) MIG v3.1 - Virtex-6: # ** Error: (vsim-8604) NaN results from division operation
(Xilinx Answer 32873) MIG v3.1 - Virtex-6 DDR2/DDR3: False memory model violations might occur in simulation
(Xilinx Answer 32830) MIG v3.1 - Virtex-6 DDR2: Master Bank must be selected in GUI even when default banks are used
(Xilinx Answer 32839) MIG v3.1 - Virtex-6 DDR2/DDR3: Non-zero values for Additive Latency are not supported
(Xilinx Answer 32870) MIG v3.1 - Virtex-6 QDRII+ SRAM: MIG does not properly restrict Data Read group bank selection which could result in "ERROR: Place:906 during MAP..."
(Xilinx Answer 32868) MIG v3.1 - Virtex-6: Enabling KEEP_HIERARCHY option in synthesis causes ERROR:PhysDesignRules:368 during BitGen
(Xilinx Answer 32930) MIG v3.1, Virtex-6 DDR3 - Changes required to simulation testbench (sim_tb_top.v) to skip calibration and avoid memory overflow errors
(Xilinx Answer 32925) MIG v3.1, Virtex-6 QDRII+ - Issues exist in calibration logic that require an updated phy_read_stage1_cal.v module

CORE Generator POS PHY Lite
(Xilinx Answer 32920) SPI-4.2 Lite v5.1 - Virtex-6 design might fail timing in PAR

MPMC
(Xilinx Answer 32861) 11.2 EDK, MPMC v5.02.a - ERROR:EDK:3193 C_MEM_PARTNO (mpmc) The parameter C_MEM_PARTNO=<part> is not found in the memory database

Clocking Wizard
(Xilinx Answer 32966) 11.2 Clocking Wizard - Virtex-6 MMCM COMPENSATION attribute must be set to ZHOLD

CORE Generator PCI Express
(Xilinx Answer 32742) Virtex-6 - Integrated Block Wrapper v1.2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.2
(Xilinx Answer 32914) Virtex-6 - Integrated Block Wrapper v1.2 for PCI Express - Error in generating core from ISE New source Wizard
(Xilinx Answer 32915) Virtex-6 - Integrated Block Wrapper v1.2 for PCI Express - Use of trn_rnp_ok_n not supported for the 8-lane Gen 2 Integrated Block Mode
(Xilinx Answer 32918) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - In x8 Gen 2 mode, trn_reof_n may assert without an associated trn_rsof_n assertion on
(Xilinx Answer 32921) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - In x8 Gen 2 Mode, using 512 byte MPS may cause Timing Failures
(Xilinx Answer 32923) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - Programmed Power Management Mode (PPM) L1 State not supported in x8 Gen 2 Mode
(Xilinx Answer 32931) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - Non-default User Interface Frequency not supported when the ML605 Development Board Option is selected
(Xilinx Answer 32932) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - VHDL Example Design and Testbench not available
(Xilinx Answer 32933) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - Root Port Operation not supported in this release
(Xilinx Answer 32934) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - 250 MHz Reference Clock required for GEN 2 Mode of Operation
(Xilinx Answer 32935) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - Incorrect Path to UCF file in implement.bat file

General Known Issues not specifically related to Virtex-6 FPGA

For ISE Design Suite Known issues, see (Xilinx Answer 32147).

For Known Issues related to specific IP, see the IP Release Notes:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
AR# 32929
日期 06/29/2010
状态 Active
Type 已知问题
器件 More Less