AR# 32958


MIG Virtex-5 FPGA QDR-II SRAM - What is the Virtex-5 FPGA QDR-II SRAM write latency?


The Memory Interface Generator Solutions User Guide (UG086) contains a table detailing the read latency for a Virtex-5 FPGA QDR-II interface.

What is the corresponding write latency?


The write command latency is a total of seven cycles from the time a request is made to the User Interface (UI), to the time the write command is sent to the memory.

Five of these cycles are consumed in the UI, so without the UI, the latency from the time the controller issues the write request to the time it is sent to the memory is two cycles.
AR# 32958
日期 09/12/2014
状态 Active
Type 综合文章
器件 More Less
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