AR# 32967

描述

During the synthesis stage, a control signal is optimized causing the netlist simulation to fail in Spartan-6. The functional simulation works fine.

解决方案

This issue is scheduled to be fixed in EDK 11.3. 

EDK 11.3 is available at:  

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp