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AR# 32975

ISE Design Suite 11.2 XST - " ERROR:HDLCompiler:410 - ".vhd" Line xx: Expression has x elements; expected y"

描述

当我指向 Virtex-6 / Spartan-6 器件时,我收到以下错误信息,但当指向老器件时,相同的代码出现警告。 

如何解决此问题?

ERROR:HDLCompiler:410 - "<file>.vhd" Line xx: Expression has x elements ; expected y 

范例代码:

 

library ieee; 

use ieee.std_logic_1164.all; 

use ieee.numeric_std.all; 

 

entity ex_0006 is 

port(a,b : in unsigned (7 downto 0); 

res : out unsigned (8 downto 0)); 

end ex_0006; 

 

architecture beh of ex_0006 is 

begin 

 

res <= a + b; -- Note: Error points here 

 

end beh;

解决方案

以上代码不与 VHDL LRM 兼容。

使用 numeric_std 包中的 resize 函数,调整左边和右边的任务以解决错误。 

 

library ieee; 

use ieee.std_logic_1164.all; 

use ieee.numeric_std.all; 

entity ex_0006 is 

port(a,b : in unsigned (7 downto 0); 

res : out unsigned (8 downto 0)); 

end ex_0006; 

 

architecture beh of ex_0006 is 

begin 

 

res <= resize(a,9) + resize(b,9); -- Note: Error points here 

 

end beh; 

 

ISE Design Suite 11.2 XST 推出了一个面向 Virtex-6 和 Spartan-6 系列的全新 VHDL/ Verilog 分析程序。


了解更多信息,敬请参考 (Xilinx 答复 32927)

AR# 32975
日期 02/27/2015
状态 Active
Type 综合文章
Tools
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • More
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
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