.vhd" Line xx: Net abcd[x] is constantly driven from multiple places"">


We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32979

11.2 XST - "ERROR:HDLCompiler:637 - ".vhd" Line xx: Net abcd[x] is constantly driven from multiple places"


I get the following error in XST when targeting Virtex-6/Spartan-6 devices, but do not have any issues when I target older devices. Why?

ERROR:HDLCompiler:637 - "<file>.vhd" Line xx: Net state[7] is constantly driven from multiple places

ERROR:HDLCompiler:208 - "<file>.vhd" Line yy: Another driver from here

Example code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity ex_0008 is

port(clk,reset : in std_logic;

output : out std_logic_vector(7 downto 0)


end ex_0008;

architecture bhv of ex_0008 is

signal state : std_logic_vector(7 downto 0);


process( reset , clk )


if(reset = '1') then

output <= "00000000";

state <= "00000000";

elsif(clk'event and clk = '1') then

case state is

when "00000000" => output <= "00000001"; state <= "00000001";

when "00000001" => output <= "00000010"; state <= "00000010";

when "00000010" => output <= "00000011"; state <= "00000011";

when others => output <= "00000100"; state <= "00000000";

end case;

end if;

end process;

state <= not state;



In the above example, signal state is assigned inside and outside the process. This description cannot be implemented in an FPGA.

The only way to solve this problem is not to assign state outside the process.

11.2 XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change, please refer to (Xilinx Answer 32927)

AR# 32979
日期 12/15/2012
状态 Active
Type 综合文章