AR# 32987

11.1 MAP, Virtex-6/ Virtex-5/ Spartan-6 - What options are available that allow two SRL16s to be combined into one LUT Complex?

描述

I would like MAP to combine two SRL16s into a single LUT Complex. How can this be done?

解决方案

For manual control of SRL16 LUT sharing, two SRL16s can be constrained to the same LUT Complex by assigning each the same LUTNM property as follows :

INST "SRL16E_0" lutnm = group_1;
INST "SRL16E_1" lutnm = group_1;

Automatic LUT sharing for SRL16s is being introduced in ISE version 11.2. The following describes the behavior of the three affected device families:

Virtex-6
Default is "AUTO", other values are "AREA" and "OFF"
The value can be changed with the following variable:
setenv XIL_MAP_SRL_COMPRESSION AREA (Linux)
SET XIL_MAP_SRL_COMPRESSION=AREA (Windows)

Spartan-6
Default is "AREA", other values are "AUTO" and "OFF"
The value can be changed with the following variable:
setenv XIL_MAP_SRL_COMPRESSION AUTO (Linux)
SET XIL_MAP_SRL_COMPRESSION=AUTO (Windows)

Virtex-5
Default is off. When turned on, this feature is equivalent to AREA mode.
The feature can be turned on with the following variable:
setenv XIL_MAP_SRL_COMPRESSION 1 (Linux)
SET XIL_MAP_SRL_COMPRESSION AUTO=1 (Windows)
NOTE: Unset the variable to turn this feature off for Virtex-5. Do not use "0" as any value is considered to be "on".

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Answer Number	问答标题	问题版本	已解决问题的版本
37213	Virtex-6 FPGA Design Assistant - Troubleshoot common fabric problems	N/A	N/A

AR# 32987
日期	12/15/2012
状态	Active
Type	综合文章
器件	Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SXT Virtex-5 TXT Virtex-5Q Virtex-5QV Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Spartan-6 LX Spartan-6 LXT More Less
Tools	ISE Design Suite - 11.1 ISE Design Suite - 11.2 ISE Design Suite - 11.3 ISE Design Suite - 11.4 ISE Design Suite - 11.5 ISE Design Suite - 12.1 ISE Design Suite - 12.2 More Less

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AR# 32987

11.1 MAP, Virtex-6/ Virtex-5/ Spartan-6 - What options are available that allow two SRL16s to be combined into one LUT Complex?

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