I have a design where I declared a component in a package the same name as one of my libraries. I get the following error with Virtex-6/Spartan-6 but do not have any issues with any of the older devices. Why?
"ERROR:HDLCompiler:40 - "<file>.vhd" Line xx: <name> is not a component"
Example code.
library ieee;
use ieee.std_logic_1164.all;
package my_pack_0002 is
component my_lib_0002
port(in_port : in std_logic;
out_port: out std_logic);
end component;
end package;
File: ex_0002.vhd
Compilation Library: work
library ieee;
use ieee.std_logic_1164.all;
library my_lib_0002;
use my_lib_0002.my_pack_0002.all;
entity ex_0002 is
port(in_port : in std_logic;
out_port: out std_logic);
end ex_0002;
architecture beh of ex_0002 is
begin
my_inst : my_lib_0002 port map(in_port =>in_port, -- Note: Error points here
out_port=>out_port);
end;
11.2 XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change, please refer to (Xilinx Answer 32927)
This is not a VHDL LRM compliant code. To solve this, simply change the name of either the library or the component.
For example, in the above code you can edit the source to:
library ieee;
use ieee.std_logic_1164.all;
package my_pack_0002 is
component my_comp_0002
port(in_port : in std_logic;
out_port: out std_logic);
end component;
end package;
File: ex_0002.vhd
Compilation Library: work
library ieee;
use ieee.std_logic_1164.all;
library my_lib_0002;
use my_lib_0002.my_pack_0002.all;
entity ex_0002 is
port(in_port : in std_logic;
out_port: out std_logic);
end ex_0002;
architecture beh of ex_0002 is
begin
my_inst : my_comp_0002 port map(in_port =>in_port, -- Note: Error points here
out_port=>out_port);
end;
| AR# 32993 | |
|---|---|
| 日期 | 12/15/2012 |
| 状态 | Active |
| Type | 综合文章 |