AR# 32996

Virtex-5/Virtex-6 GTP/GTX and Spartan-6 GTP Transceiver Wizard - Timing not met on implemented example design

描述

When RXRECCLK is used to generate RXUSRCLK, it is possible that timing will not be met upon implementation. This Answer Record discusses the issue and how to work around it.

解决方案

When RXRECCLK is used to generate RXUSRCLK or multiple reference clocks are used, it is possible for the clock supplying the automatically generated ChipScope ILA Core to fail timing. Currently, the only method for working around this problem is to remove the automatically generated ChipScope cores. The simplest way to do this is to set the EXAMPLE_USE_CHIPSCOPE parameter to 0.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
33475 Virtex-6 FPGA GTX Transceiver - Known Issues and Answer Record List N/A N/A
AR# 32996
日期 10/16/2013
状态 Active
Type 已知问题
器件 More Less
Tools