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AR# 33119

11.1 EDK, ppc440mc_ddr2 - DDR2 200 microseconds initialization time violated when TREFI is less than 7.8 microseconds

描述

When using the ppc440mc_ddr2 memory controller with a TREFI timing parameter less than 7.8 microseconds, the required 200 microseconds initialization time is violated. TREFI might need to be set to 3.9 microseconds for some industrial DDR2 parts.

This issue can lead to intermittent DDR2 device behavior. How do I resolve this issue?

解决方案

This issue is fixed in the latest ppc440mc_ddr2 core. The first version containing this fix is ppc440mc_ddr2_v2_00_b, released in EDK 11.2.

AR# 33119
日期 12/15/2012
状态 Active
Type 综合文章
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