AR# 33125: 11.4 System Generator for DSP - Why do I receive NGDBuild errors regarding illegal buffers when I generate my MPMC/EDK Processor design to a Hardware co-simulation target?
11.4 System Generator for DSP - Why do I receive NGDBuild errors regarding illegal buffers when I generate my MPMC/EDK Processor design to a Hardware co-simulation target?
Keywords: SysGen, MPMC, VFBC
When I try to generate a hardware co-sim block from my EDK Processor block design, I receive the following errors in NGDBuild:
ERROR:NgdBuild:770 - IBUFs are lined up in series. Buffers of the same direction cannot be placed in series. ERROR:NgdBuild:925 - input net 'ibuf_fpga_0_ddr2_sdram_ddr2_dqs_div_i_pin_o' is connected to the incorrect side of buffer(s): pin O on block ibuf_fpga_0_ddr2_sdram_ddr2_dqs_div_i_pin/ibuf_array.u1with type IBUF ERROR:NgdBuild:467 - output pad net 'sysgen_hwcosim_iface_fpga_0_ddr2_sdram_ddr2_addr_pin(0)' has an illegal buffer
Before attempting this solution, you should generate your hardware co-simulation block without running the script below as this does not affect all designs.
These errors might occur because the MPMC core in EDK uses the MIG physical layer which instantiates buffers directly in the source code. XST then infers additional buffers at the top level which creates duplicate buffers and causes the errors.
To work around this issue, the gateways which represent the MPMC external signals must have parameters set so that additional I/O buffers are not inferred at the top level.
The script file is called "edkprocessor_ddr2fix.m". This script sets the appropriate parameters for the example given in the Application Note and will be applicable to some MPMC designs; for others, the list of ports in the script might need to be updated to match the specific design.
NOTE: This script is not supported for FSL based peripherals. The PLB bus is now the preferred bus in System Generator.