AR# 33268


MIG Virtex-6 DDR2/DDR3 - Is it possible to combine MMCMs to save MMCM resources in multi-controller designs?


Starting in MIG 3.4, the Virtex-6 FPGA DDR3 MIG design uses one MMCM which creates all clocks used within the design. It is instantiated in the file ddrX_infrastructure.v/.vhd. For multi-controller implementation, each controller will have its own separate MMCM (that is, two controllers will use 2 MMCMs).

Prior to MIG 3.4, the design used two MMCMs for each controller (one for the write path and one for the read path). With this design technique it was possible to share the write MMCM. With the new design technique there will be less total MMCMs since each controller only uses one. All users must update to MIG 3.4.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


The MMCM used for each controller generates a 1x and 0.5x global clocks (BUFG) and 1x performance clock (CLKPERF). The .5x global clock is used to drive the user interface, the controller state machine and parts of the PHY logic. The 1x global clock drives the OSERDES for output signals going to the memory and I/O logic for the DQ and DQS groups. The 1x Performance clock drives the read synchronization and capture logic.

For a detailed block diagram see UG406 under DDR2/DDR3 > Core Architecture > PHY.

Because of the design's usage of the CLKPERF on the read path, it is not possible to share MMCM resources across multiple controllers. It is required for each controller to use a unique MMCM.



AR# 33268
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
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