AR# 33289

MIG v3.1, v3.2, v3.3, v3.4 Virtex-6 FPGA QDRII+ - Changes required to Samsung simulation model for proper operation and completion of calibration

描述

When I run a Virtex-6 FPGA MIG v3.1 QDRII+ simulation with a Samsung model (K7SXXXXT4C_R04.v), calibration does not complete (cal_done does not assert).

解决方案

Changes to the Samsung model (K7SXXXXT4C_R04.v) are required for proper simulation operation with the Virtex-6 FPGA QDRII+ design. Edit the following within the model:

Line 244 -

Change from: eclk = ~K_N;

Change to: eclk = ~K;


Line 245 -

Change from: eclk_b = ~K;

Change to: eclk_b = ~K_N;


This ensures data is presented on the correct clock. After making these changes, calibration completes successfully.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 33289
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
IP