AR# 3329

ngd2vhdl M1.3/M1.4: Why does ngd2vhdl create a data type called std_logic_vector2?


keywords:std_logic_vector2,ngd2vhdl,vhdlan,vss, vhdlan error,
vss error

urgency: standard

general description:

When ngd2vhdl creates an HDL file for simulation, a data
type called std_logic_vector2 is sometimes used.

std_logic_vector2 is a VHDL data type defined by the
Xilinx simulation libraries.This datatype can be found
in VHDL files created by ngd2vhdl. ngd2vhdl uses the
std_logic_vector2 data type if the original design contained
2-dimensional arrays.

The std_logic_vector2 data type is defined in the VITAL
libraries in M1.3/M1.4.When the VHDL file from ngd2vhdl
contains the data type std_logic_vector2, and a VHDL
simulator that analyzes the VHDL from ngd2vhdl errors,
and says that the data type std_logic_vector2 is undefined,
this means that the VITAL libraries are not setup
correctly with the VHDL simulator.




AR# 3329
日期 04/06/2000
状态 Archive
Type 综合文章