AR# 33408

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11.3 EDK, plbv46_pcie_v4_01_a - Bridge does not complete the PLB to PCIe write request and hangs

描述

In the test_hello_world, the Virtex-6 FPGA End Point bridge receives a PCIe to PLB write request at the same time as a PLB to PCIe write request. The PLB to PCIe write request is never completed on the PLB and hangs the bus. The PCIe to PLB write request never goes through the bridge. Previous to this, there is a PCIe to PLB read request that completes correctly.

解决方案

This has been fixed in the latest PLBv46_pcie core, and is available in EDK 11.3. 

EDK 11.3 is available at:  

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
AR# 33408
日期 05/23/2014
状态 Archive
Type 综合文章
Tools
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