AR# 33417

描述

The Spartan-6 FPGA Memory Controller User Guide (ug388) states the following in the Getting Started section: 

The bitstream created from this example design flow can be targeted to a Spartan-6 FPGA SP601 or SP605 hardware evaluation board to demonstrate DDR2 or DDR3 interfaces, respectively. 

 This statement is not fully accurate as the clock and reset pin assignments in the MIG output UCF do not match the pins on the SP601 and SP605 boards.

解决方案

To work around this, modify the clock and reset pin assignments in the output UCF file to the appropriate pins for the targeted reference board. 

MIG v3.3, released with IDS 11.4, will assign the appropriate clock and reset pins associated with the SP601 and SP605 boards.