UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33440

MIG v3.2-3.61 Virtex-6 DDR2 - When ODT is disabled (RTT_NOM = 0), ODT is incorrectly asserted immediately following calibration

描述

When ODT is disabled (RTT_NOM), the ODT pin is expected to be held LOW until an EMRS command is applied to enable ODT.

The MIG Virtex-6 FPGA DDR2 design incorrectly asserts the ODT signal after the design completes calibration.

解决方案

Because the controller programmed the memory with ODT disabled, the memory ignores the ODT toggling.

This does not cause any issues in simulation or hardware.

This can be fixed by opening sim_tb_top.v/vhd, example_design.v/vhd, and the User Design top-level <your_design_name>.v/vhd and setting RTT_NOM="DISABLED".

This issue is fixed in the ISE 13.1 MIG v3.7 software release.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
38951 MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2 N/A N/A
AR# 33440
日期 08/14/2014
状态 Active
Type 综合文章
器件
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG
的页面