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AR# 33535

11.1 EDK, PPC440MC_DDR2 - "ERROR:Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=PPC440_X0Y0)..."


Keywords: IP, memory

When the PPC440 debug halt signals are connected along with the PPC440MC_DDR2 memory controller, the following error occurs.

ERROR:Pack:2811 - Directed packing was unable to obey the user design
constraints (LOC=PPC440_X0Y0) which requires the combination of the symbols
listed below to be packed into a single component.

The directed pack was not possible because: Two or more symbols must target
conflicting component types. Please correct the design constraints

The symbols involved are:
LUT symbol "ppc440_0/ppc440_0/DBGC440DEBUGHALT_i1" (Output Signal =
PPC440 symbol "ppc440_0/ppc440_0/PPC440_i" (Output Signal = NULL)

How do I resolve this error?


This issue is caused by the optimal PPC440MC_DDR2 UCF files containing the following constraint placed on the entire PPC440 pcore, instead of the actual PPC440 component. Some additional logic can be connected when debug ports are connected, which cannot be placed at the PPC440 site.

To work around this issue, in the UCF, modify the instance name of the PPC440 LOC constraint to be the actual name of the PP440 primitive.

For example:
INST "*/PPC440_i" LOC = PPC440_X0Y0;

The provided optimal PPC440MC_DDR2 UCF files will be updated to use the correct instance name starting in EDK 11.4.
AR# 33535
日期 09/22/2009
状态 Active
Type 综合文章