AR# 33566

Design Advisory Master Answer Record for Programmable Logic Based External Memory Interface Solutions for Virtex-6, Spartan-6, all 7 Series Devices, and all UltraScale based Devices

描述

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. 
 
This Design Advisory Master Answer Record covers the programmable logic based external memory interface IPs from 6 Series through to UltraScale based devices. 
This includes the supported memory IPs such as DDR2, DDR3, DDR4, LPDDR2, and LPDDR3 as well as SRAM based solutions like QDR and RLDRAM.

解决方案

UltraScale MIG

The UltraScale/UltraScale+ Memory IP Master Release Notes and Know Issues can be found in (Xilinx Answer 58435)

 

UltraScale Memory Design Hubs:

03/26/2020(Xilinx Answer 73068)Design Advisory for UltraScale/UltraScale+ DDR4/DDR3 IP - Memory IP Timing Exceptions can Manifest as Post Calibration Data Errors or DQS Gate Tracking Errors in Hardware
12/20/2016(Xilinx Answer 68169)Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs - New minimum production speed specification version (Speed File) required for all designs
07/06/2015(Xilinx Answer 64856)Design Advisory for UltraScale DDR4/DDR3 - PCB pull-down required on the DDR3 RESET# pin and on the DDR4 RESET_N pin to maintain logic low during memory initialization
10/27/2014(Xilinx Answer 62483)Design Advisory for MIG UltraScale (all memory types) - VRP pin required for all I/O banks including output only banks
10/13/2014(Xilinx Answer 62157)Design Advisory for MIG UltraScale QDRII+ - pinout DRC violations not caught in I/O Planner

7 Series DDR3 MIG  

The 7 Series Memory IP Master Release Notes and Know Issues can be found in (Xilinx Answer 54025)

03/23/2016(Xilinx Answer 66788)Design Advisory for MIG 7 Series DDR3 - DQS_BIAS is not properly enabled for HR banks causing potential calibration failures
11/23/2015(Xilinx Answer 65414)Design Advisory for MIG 7 Series QDRII+, RLDRAM3, RLDRAM2 - Calibration updates in MIG 7 Series v2.4 available with Vivado 2015.3 provide additional write and read margin
10/12/2015(Xilinx Answer 59167)Updated Design Advisory for MIG 7 Series DDR3 - Data rate specification changes for DIMM interfaces and data rate advisory for component interfaces
11/19/2014(Xilinx Answer 62368)Design Advisory for MIG 7 Series DDR3 - Calibration updates in MIG 7 Series v2.3 available with Vivado 2014.4 provide additional write margin
06/11/2014(Xilinx Answer 60845)Design Advisory for MIG 7 Series RLDRAM3 - SIM_BYPASS_INIT_CAL incorrectly set to "FAST" for synthesis and implementation
06/02/2014(Xilinx Answer 59167)Design Advisory for MIG 7 Series DDR3 - Data rate specification changes for DIMM interfaces and data rate advisory for component interfaces
11/11/2013(Xilinx Answer 58172)Design Advisory for MIG 7 Series DDR3/DDR2 - MIG includes incorrect maximum frequencies for 2:1 (half-rate) DDR3/DDR2 controller designs targeting -2 and -1 speed grades. Maximum spec numbers in datasheets are correct.
04/22/2013(Xilinx Answer 55531)Design Advisory for MIG 7 Series v1.9 DDR3/DDR2 - PRBS Calibration results are not applied. RTL Updates Required.
04/22/2013(Xilinx Answer 55536)Design Advisory for MIG 7 Series LPDDR2 - MIG allows incorrect placement of CK/CK# pairs when using the "Verify Pin Changes and Update Design" and "Fixed Pin-Out" flows. Documentation and "New Design" flow are correct.
01/28/2013(Xilinx Answer 53860)Design Advisory for MIG 7 Series DDR3 - All CK clock pins must to be in the same byte lane/group. Validating Dual Rank Pin-Outs Required.
01/28/2013(Xilinx Answer 53919)Design Advisory for MIG 7 Series v1.8 RLDRAM II - Pinout violation not detected in "Fixed Pin Out" mode or "Verify Pin Changes and Update Design" flow.
01/21/2013(Xilinx Answer 53607)Design Advisory for MIG 7 Series QDRII+ - Inferred latches cause write calibration failures. Work-around required.
01/07/2013(Xilinx Answer 53420)Design Advisory for MIG 7 Series DDR3/DDR2 - Required calibration patch for v1.7 and v1.8
12/10/2012(Xilinx Answer 53053)Design Advisory MIG 7 Series QDRII+ - Read calibration failures can occur when CPT_CLK_CQ_ONLY=FALSE
10/24/2012(Xilinx Answer 52573)Design Advisory MIG 7 Series DDR3 - Issue with OCLKDELAY calibration causes write DQS to be aligned to DQ with potential calibration failures
10/24/2012(Xilinx Answer 51687)Design Advisory MIG 7 Series DDR3/DDR2 - Temperature monitor calibration using XADC block added to all DDR3/DDR2 designs in v1.7 (ISE 14.3/Vivado 2012.3)
08/20/2012(Xilinx Answer 51296)Design Advisory - 7 Series Package Flight Time Changes in ISE 14.2 and Vivado 2012.2 Design Suite Releases
08/06/2012(Xilinx Answer 50461)Design Advisory MIG 7 Series v1.6 - Calibration updates for all interfaces
05/14/2012(Xilinx Answer 47043)Design Advisory MIG 7 Series - Addition of MMCM to clocking structure starting with v1.5 (available with ISE Design Suite 14.1)
01/10/2012(Xilinx Answer 45633)Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified
05/05/2011(Xilinx Answer 42036)7 Series MIG DDR3 - Internal/External Vref Guidelines
04/11/2011(Xilinx Answer 40876)MIG 7 Series 1.1 DDR3 SDRAM - MIG allows setting memory frequencies above data sheet specifications

Spartan-6 FPGA MCB


  • Legacy release notes for 6-Series based IP and ISE based releases can be found in XTP025
  • For legacy MIG releases general design and troubleshooting information can be found in the Xilinx MIG Solution Center at: (Xilinx Answer 34243)
04/18/2011(Xilinx Answer 41520)Spartan-6 MCB Design Advisory - Removal of VCCINT restrictions to reach maximum DDR3 data rates
11/09/2010(Xilinx Answer 36291)MIG, MPMC, Spartan-6 MCB - Memory failures occur on initial configuration.
06/14/2010(Xilinx Answer 35976)MIG Spartan-6 MCB - Design does not come out of reset and requires power-cycle to regain functionality - SW / IP update required.
06/14/2010(Xilinx Answer 35818)Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 and DDR3 interfaces.
02/08/2010(Xilinx Answer 34165)MIG v3.3, Spartan-6 FPGA MCB - Incorrect port connection causes Continuous DQS Tuning to behave incorrectly - Manual modification required.
02/08/2010(Xilinx Answer 34046)MIG v3.3, Spartan-6 FPGA LPDDR - Calibrated and Un-Calibrated Input Termination features not supported.
02/08/2010(Xilinx Answer 34055)MIG v3.3, Spartan-6 FPGA MCB - What are the requirements for the RZQ and ZIO pins?
02/08/2010(Xilinx Answer 34137)MIG v3.3, Spartan-6 FPGA LPDDR - Drive strength selected in MIG is not properly set in the output design.
02/08/2010(Xilinx Answer 34089)MIG v3.3, Spartan-6 FPGA MCB - Some bits of the MCB address bus (mcbx_dram_addr) may violate the input hold time (tIH) specification of the memory device.
09/23/2009(Xilinx Answer 33358)Spartan-6 FPGA MCB - Data Mask cannot be disabled and the UDM and LDM pins cannot be used as General Purpose I/O (GPIO).

 

Virtex-6 DDR2/DDR3 MIG

  • Legacy release notes for 6-Series based IP and ISE based releases can be found in XTP025
  • For legacy MIG releases general design and troubleshooting information can be found in the Xilinx MIG Solution Center at: (Xilinx Answer 34243)
03/9/2010(Xilinx Answer 34204)MIG v3.0-3.3, Virtex-6 FPGA DDR3/DDR2 - Read Leveling Stage 2 fails in hardware due to OCB Monitor issue.
02/8/2010(Xilinx Answer 33995)MIG 3.3, Virtex-6 FPGA DDR3 - Write Leveling does not succeed and calibration fails due to IDELAYCTRL not being automatically inferred by the software.
02/8/2010(Xilinx Answer 34094)MIG v3.3, Virtex-6 FPGA DDR2/DDR3- MMCM CLKFBOUT_MULT_F= 4 not valid, manual modification required

 

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https://www.xilinx.com/myprofile/doc-alerts.html

 

Revision History

03/26/2020Added 73068
12/09/2019Added links to 7 Series and UltraScale resources, updated formatting
03/08/2017Added 60845, 65414, 66788, 68169
10/12/2015Added update to 59167
07/06/2015Added 64856
10/22/2014Added 62483 and 62157
06/04/2014Added 59167
11/11/2013Added 58172
04/18/2013Added 55531 and 55536
01/28/2013Added 53919 and 53860
01/21/2013Added 53607
01/07/2013Added 53420
12/10/2012Added 53053
10/24/2012Added 51687 and 52573
08/20/2012Added 51296
08/06/2012Added 50461
05/14/2012Added 47043
03/12/2012Added updated patch for 45653
02/23/2012Added 45653
01/10/2012Added 45633
05/05/2011Updated 7 Series DDR3 MIG to include 42036
05/02/2011Updated 7 Series DDR3 MIG to include 41981
04/18/2011Updated Spartan-6 list to include 41520
04/11/2011Added 7 Series and included 40876 and 41351 (Since obsoleted)
11/09/2010Updated Spartan-6 list to include 36291
06/14/2010Updated Spartan-6 list to include 35978, 35976, and 35818
03/09/2010Updated list to include 34204
02/08/2009Updated list to include 34165, 34046, 34055, 34137, 34089, 33995, and 34094
09/28/2009Initial Release; added 33358

链接问答记录

主要问答记录

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
45633 关于 7 系列 MIG DDR3/DDR2 设计咨询 - 针对 CKE 和 ODT 的更新引脚布局规则;必须验证现有的 UCF N/A N/A
53053 有关 MIG 7 系列 QDRII+ 的设计咨询 - 当出现 CPT_CLK_CQ_ONLY=FALSE 时,会发生读取校准故障 N/A N/A
51296 设计咨询 - ISE 14.2 和 Vivado 2012.2 Design Suite 版本中 7 系列包延迟时间 (Package Flight Time) 的改变 N/A N/A
35976 MIG、MPMC 和 Spartan-6 MCB 的设计咨询 - 设计不是通过复位产生的,需要重新上电才能恢复功能性(需要软件/IP 核升级) N/A N/A
47043 MIG 7 系列设计咨询——向 1.5 版以上的时钟结构(ISE Design Suite 14.1可提供)添加 MMCM N/A N/A
41520 面向 Spartan-6 MCB 的设计咨询 - 取消 VCCINT 限制以达到最大 DDR3 数据速率 N/A N/A
35818 Design Advisory for Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 Interfaces N/A N/A
34204 MIG v3.0-3.3, Virtex-6 DDR3/DDR2 - Read Leveling Stage 2 fails in hardware due to OCB Monitor issue N/A N/A
50461 有关 MIG 7 系列 v1.6 的设计咨询 - 所有接口的校正更新 N/A N/A
58172 面向 MIG 7 系列 DDR3/DDR2 的设计咨询 - MIG 包括面向 -2 / -1 速度级 2:1 (半速) DDR3/DDR2 控制器设计的错误最大频率; 数据表列出的最大规范值是正确的。 N/A N/A
59167 面向 MIG 7 系列 DDR3 的设计咨询 - DIMM 接口的数据速率规范更改和组件接口的数据速率咨询 N/A N/A
62483 MIG UltraScale 设计咨询(所有存储器类型)— VRP 引脚及 DCI 级联要求 N/A N/A
64856 UltraScale DDR4/DDR3 的设计咨询 — DDR3 RESET# 引脚和 DDR4 RESET_N 引脚上所需的 PCB 下拉可在存储器初始化期间保持逻辑低电平 N/A N/A
66788 Design Advisory for MIG 7 Series DDR3 - DQS_BIAS is not properly enabled for HR banks causing potential calibration failures N/A N/A
60845 Design Advisory for MIG 7 Series RLDRAM3 - SIM_BYPASS_INIT_CAL incorrectly set to "FAST" for synthesis and implementation N/A N/A
65414 Design Advisory for MIG 7 Series QDRII+, RLDRAM3, RLDRAM2 - Calibration updates in MIG 7 Series v2.4 available with Vivado 2015.3 provide additional write and read margin N/A N/A
68169 Kintex UltraScale FPGA 和 Virtex UltraScale FPGA 的设计咨询 — 所有设计所需的最新最低生产速度规范版本(速度文件) N/A N/A
73068 面向 UltraScale/UltraScale+ DDR4/DDR3 IP 的设计咨询 - 存储器 IP 时序异常可能导致校准后硬件中出现数据错误或 DQS 门控跟踪错误 N/A N/A

相关答复记录

AR# 33566
日期 08/25/2020
状态 Active
Type 设计咨询
器件 More Less
Tools
IP More Less