AR# 33571

11.1 Virtex-6 FPGA Editor - The first time I bring up a component in Logic Block Editor, the Attributes and Nets do not appear


I have a Virtex-6 design which I am looking at in FPGA Editor. The first time I open a component in Logic Block Editor, it appears unused. None of the connections nor attributes appear. 


How do I get around this?


This will be resolved in a future version of software. 


To work around this in current software, close the Logic Block Editor and reopen it. Everything will appear normally when reopened.



AR# 33571
日期 05/23/2014
状态 Archive
Type 综合文章