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AR# 33643

Endpoint Block Plus Wrapper v1.12 for PCI Express - Cannot implement the core in Project Navigator

描述


When I import all the files required to implement the PCIe BP v1.12 design into ISE Project Navigator, an error message is generated during synthesis:



ERROR:HDLCompilers:91 - "../../../endpoint_blk_plus_v1_12/source/pcie_ep.v" line 1134 Module 'pcie_blk_if' does not have a port named 'cfg_interrupt_assert_n'

ERROR:HDLCompilers:91 - "../../endpoint_blk_plus_v1_12/source/pcie_ep.v" line 1135 Module 'pcie_blk_if' does not have a port named 'cfg_interrupt_di'

解决方案

;
To work around this issue, go to the Synthesis properties and change the Property Display Level to "Advanced".



In switch '-define' (Verilog Macros), add following:



NEWINTERRUPT=b1 | USE_PLL=b1



Revision History

10/26/2009 - Initial Release
AR# 33643
日期 08/06/2010
状态 Active
Type ??????
IP
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