This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP Image Edge Enhancement.
The following information is listed for each version of the core:
LogiCORE IP Image Edge Enhancement Product Page:
https://www.xilinx.com/products/intellectual-property/ef-di-img-enhance.html
| (Xilinx Answer 34828) | How do I simulate my Video IP pCore in EDK? |
| N/A |
| (Xilinx Answer 57773) | Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation? |
| (Xilinx Answer 52215) | Why does my core fail timing with a Critical Warning? |
| (Xilinx Answer 57773) | Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation? |
LogiCORE IP Image Edge Enhancement v5.01.a
| (Xilinx Answer 51589) | Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
| (Xilinx Answer 60173) | Why does the Image Enhancement core output data in the wrong columns after changing the number of columns via the AXI4-Lite interface? |
| (Xilinx Answer 57773) | Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation? |
| (Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
| (Xilinx Answer 60173) | Why does the Image Enhancement core output data in the wrong columns after changing the number of columns via the AXI4-Lite interface? |
| (Xilinx Answer 57773) | Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation? |
LogiCORE IP Image Edge Enhancement v5.00.a
| (Xilinx Answer 51589) | Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
| (Xilinx Answer 33872) | "ERROR: simAn IP generation script exited abnormally. Error found during generation." |
| (Xilinx Answer 35130) | Why do I get the following error when generating with a Design Linking License? ERROR: simError: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWritersUG:380The design contains secured core. |
| (Xilinx Answer 35437) | Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name? |
Bug Fixes
| (Xilinx Answer 33872) | "ERROR: simAn IP generation script exited abnormally. Error found during generation." |
| (Xilinx Answer 35130) | Why do I get the following error when generating with a Design Linking License? ERROR: simError: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380The design contains secured core. |
| (Xilinx Answer 35437) | Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name? |
New Features
| (Xilinx Answer 33872) | "ERROR: simAn IP generation script exited abnormally. Error found during generation." |
| (Xilinx Answer 35130) | Why do I get the following error when generating with a Design Linking License? ERROR: simError: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380The design contains secured core. |
| (Xilinx Answer 35437) | Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name? |
| (Xilinx Answer 37987) | Where can I find the Xilinx Streaming Video Interface User Guide(UG762)? |
| AR# 33749 | |
|---|---|
| 日期 | 08/03/2018 |
| 状态 | Archive |
| Type | 版本说明 |
| IP | |