AR# 33761

Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - How to enable use of a 100 MHz reference clock

描述

The v1.2 release allows the use of a 125 MHz reference clock. A 100 MHz reference clock is also supported.

解决方案

Enabling the use of a 100 MHz reference clock requires some modification to the generated wrapper files. This requirement goes away in the v1.3 release coming in ISE software 12.1.

To use a 100 MHz reference clock, the v1.2 release must be used; it is not supported with v1.1.

Verilog Design Flow:

  1. Open < core_name. v> file which is located in < core_name >/source directory
    a. Modify line 139 parameter REF_CLK_FREQ to 0
    b.Modify line51 REF_CLK_FREQ to 0
  2. Open "gtpal_dual_tile.v" file which is located in < core_name >/source directory
    a.If using channel _0 of the GT Dual tile, modify the following lines:
    i.Line 261 change CLK25_DIVIDER_0 value from 5 to 4
    ii.Line 267 change PLL_DIVSEL_FB_0 value from 2 to 5
    iii.Line 268 change PLL_DIVSEL_REF_0 value from 1 to 2
    b.If using channel _1 of the GT Dual tile, modify the following lines:
    i.Line 274 change CLK25_DIVIDER_1 value from 5 to 4
    ii.Line 282 change PLL_DIVSEL_FB_1 value from 2 to 5
    iii.Line 283 change PLL_DIVSEL_REF_1 value from 1 to 2
  3. Open the UCF file and update the clock constraint to 100 MHz. You perform this by changing the clock from 8ns to 10ns.
    a. Line 127- NET sys_clk_c PERIOD = 10ns;
    b. Line 130- TIMESPEC TS_GT_REFCLK_OUT = PERIOD GT_REFCLK_OUT 10ns HIGH 50%

VHDL Design Flow:

  1. Open < core_name.vhd > file which is located in < core_name >/source directory
    a. Modify line 149 parameter REF_CLK_FREQ to 0
    b. Modify line243 REF_CLK_FREQ to 0
  2. Open "Xilinx_pcie_1_1_ep_s6.vhd" file which is located in < core_name >/example_design directory
    a. Modify line 240 REF_CLK_FREQ to 0
  3. Open "gtpal_dual_tile.vhd" file which is located in < core_name >/source directory
    a. If using channel _0 of the GT Dual tile, modify the following lines:
    i.Line 260 change CLK25_DIVIDER_0 value from 5 to 4
    ii.Line 266 change PLL_DIVSEL_FB_0 value from 2 to 5
    iii.Line 267 change PLL_DIVSEL_REF_0 value from 1 to 2
    b. If using channel _1 of the GT Dual tile, modify the following lines:
    i.Line 273 change CLK25_DIVIDER_1 value from 5 to 4
    ii.Line 281 change PLL_DIVSEL_FB_1 value from 2 to 5
    iii.Line 282 change PLL_DIVSEL_REF_1 value from 1 to 2
  4. Open the UCF file and update the clock constraint to 100 MHz. You can perform this by changing the clock from 8ns to 10ns.
    a. Line 127- NET sys_clk_c PERIOD = 10ns;
    b. Line 130 -TIMESPEC TS_GT_REFCLK_OUT = PERIOD GT_REFCLK_OUT 10ns HIGH 50%

For more information about clocking Xilinx devices for PCI Express, see (Xilinx Answer 18329).

Revision History
07/05/2011 - Updated title
04/06/2010 - Added VHDL flow vs Verilog flow
12/09/2009 - Added UCF constraints
11/11/2009 - Fixed PLL_DIVSEL_REF_0 value. Should be 2 not 0
11/05/2009 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
33776 Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper for PCI Express Master Answer Record N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
33776 Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper for PCI Express Master Answer Record N/A N/A
AR# 33761
日期 05/22/2012
状态 Active
Type 设计咨询
IP