AR# 33808

SPI-3 Link Layer v7.1 - "ERROR:Pack:1653 - At least one timing constraint is impossible to meet.."

描述

The following Map error may occur even after modifying the DCM Phase Shift value as per (Xilinx Answer 34527) in ISE 11.4 or earlier:

"ERROR:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint."

解决方案

This issue has been fixed in ISE design tools 11.5.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
32651 Spartan-6 — ISE 软件 11 与 Spartan-6 FPGA 有关的已知更新问题 N/A N/A
AR# 33808
日期 05/19/2012
状态 Archive
Type 已知问题