Why do I receive block RAM collision errors in my simulation?
"Error: Memory Collision Error on RAMB16BWER ::v_stats_v1_0_tb:sysgen_dut:blk000015af: at simulation time ...... ns.
A read was performed on address 00xx (hex) of port B while a write was requested to the same address on Port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle."
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
33748 | LogiCORE IP Image Statistics - Release Notes and Known Issues | N/A | N/A |
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
33748 | LogiCORE IP Image Statistics - Release Notes and Known Issues | N/A | N/A |
AR# 33848 | |
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日期 | 07/20/2012 |
状态 | Archive |
Type | 版本说明 |
IP |