2. 技术支持
  3. AR# 3384: XABEL M1.3 - Slew rate property does not work with EPLD patches
  4. AR# 33848: LogiCORE IP Image Statistics v1.0 - Why do I receive block RAM collision errors in my simulation?

AR# 33848

LogiCORE IP Image Statistics v1.0 - Why do I receive block RAM collision errors in my simulation?

描述

Why do I receive block RAM collision errors in my simulation?

"Error: Memory Collision Error on RAMB16BWER ::v_stats_v1_0_tb:sysgen_dut:blk000015af: at simulation time ...... ns.

A read was performed on address 00xx (hex) of port B while a write was requested to the same address on Port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle."

解决方案

This is a known problem with simulation that isfixed in ISE Design Suite 12.3. It isno longer a problem in the Image Statistics v4.0. This does not affect the hardware because the outputs for the block RAM are not being used at the time the collision occurs.

For a detailed list of LogiCORE Image Statistics Release Notes and Known Issues, see (Xilinx Answer 33748).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
33748 LogiCORE IP Image Statistics - Release Notes and Known Issues N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
33748 LogiCORE IP Image Statistics - Release Notes and Known Issues N/A N/A
AR# 33848
日期 07/20/2012
状态 Archive
Type 版本说明
IP