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AR# 33888

LogiCORE IP Display Port v1.2 - The example design does not meet timing when I target a Spartan-6 device. Why?

描述

Why does the example design fail to meet timing when I target a Spartan-6 device?

解决方案

The timing for the Spartan-6 device is very tight and requires the use of area constraints in order to meet timing. 

There are some constraints in the example design UCF to help meet timing, however in some cases the user will need to modify the area constraints to meet timing. 

You can modify the constraints using the PlanAhead tool, or by editing the UCF file in a text editor. 

You can also change the map options (-register_duplication, -logic_opt, -retiming), or apply an area group.

For a detailed list of LogiCORE IP Display Port Release Notes and Known Issues, see (Xilinx Answer 33258).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
35180 Spartan-6 - 12.4 Software Known Issues related to the Spartan-6 FPGA N/A N/A
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A
AR# 33888
日期 08/05/2014
状态 Archive
Type 综合文章
IP
  • DisplayPort
的页面