UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 3389

M1 docs., library guide,X74_168: Fig. 12.12, shown cascading counter is wrong.

Description

Keywords: carry, logic, cascade, x74_168, 74168

Urgency: Standard

General Description:
Fig. 12-12 in M1 documentation CD shows how to cascade x74_168
with carry lookahead.

The figure is wrong.
ENP of the first stage and ENT of the second
stage should be connected to GND.

The connection shown is to VCC. With this connection, the
counter will not count up/down.

解决方案

Change the ENP of the first stage and ENT of the second
stage connection to GND.
AR# 3389
创建日期 02/05/1998
Last Updated 05/31/2002
状态 Archive
Type 综合文章