The CCLK pin is a dedicated configuration pin. This pin can also be driven by the user design after configuration by using the STARTUP block.
This is not applicable for Spartan devices as the CCLK pin is User I/O after configuration and is not a dedicated pin.
In order to drive CCLK during post-configuration, connect a signal to the USRCCLKO input port of the STARTUP primitive and drive USRCCLKO High (to drive CCLK High) or Low (to drive CCLK Low). This will allow the fabric to control the tri-state and output signal for the pin.
The CCLK output is not valid until after the End of Startup (EOS) which is typically a couple CCLK cycles after the design becomes functional. The design will be enabled in the startup sequence by the GTS and GWE signals which typically occurs on states 5 and 6 of the startup sequence. The EOS signal will be enabled on state 8, so there might be a couple CCLK cycles where the design is functional and CCLK is not being driven by the design.
Sample VHDL to drive the CCLK pin on the device from the STARTUP block is as follows for a V-5 device:
entity startup is
dummy: out std_logic);
architecture startup_arch of startup is
signal myeos : std_logic;
signal myclk : std_logic;
signal shiftclk : std_logic_vector(127 downto 0) := X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
dummy <= myeos;
if (rising_edge(myclk)) then
if (myeos='1') then
shiftclk <= '0' & shiftclk(127 downto 1);
STARTUP_VIRTEX5_inst : STARTUP_VIRTEX5
port map (
EOS => myeos,
CFGMCLK => myclk,
USRCCLKO => shiftclk(0), -- User CCLK 1-bit input
USRCCLKTS => '0'