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AR# 33909

11.3 System Generator for DSP - Why do I sometimes see cycle mismatches between my Simulink and HDL simulations when I use a really small sample period?

描述

When I use a small sample period on the order of my actual clock, I sometimes see different latencies and results than expected.

解决方案

This is because of a known issue with the way System Generator interacts with the Simulink solver.  

 

To work around this issue, it is recommended that you use normalized integer rates, such as normalizing all your clocks to a period of 1. 

 

This issue has been resolved in System Generator 11.4.

AR# 33909
日期 05/23/2014
状态 Archive
Type 综合文章
的页面