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  3. AR# 34019: ISE Design Suite 11.4.1 - Known Issues for Virtex-6 FPGA Service Pack

AR# 34019

ISE Design Suite 11.4.1 - Known Issues for Virtex-6 FPGA Service Pack

描述

ISE Design Suite 11.4.1 is alimited release thatis for customers who have received Production6VLX240T silicon only. If you have further questions, please contactTechnical Support. Critical: You must rerun your design through the implementation tools after installing ISE Design Suite 11.4.1.

Certain IP products may error during implementation due to new requirements on the Virtex-6 FPGA MMCM attribute settings. See Xilinx Answer 33849 which is also listed below for more information.

Please note that the 6VLX240T speeds filesincluded in this update have been verified against production silicon and are now labeled "PRODUCTION." However, full hardware validationof IP coresis NOT available for ISE Design Tools 11.4.1. If you experience issues with IP Cores, please reference theKnown Issues section of this Answer Record.Bug fixes for most issueswill be in a future ISE Design Suite update(currently scheduled for March2010).

解决方案

Known Issues:

Critical

(Xilinx Answer 33849) Virtex-6 FPGA MMCM - New Requirements for DRP/Phase Shift, VCO minimum frequency, and CLKFBOUT_MULT_F values

General
(Xilinx Answer 32929) Virtex-6 - 11.x Software Known Issues related to the Virtex-6 FPGA

PCI Express
(Xilinx Answer 34146) Virtex-6 Integrated Block Wrapper v1.4 for PCI Express - Timing Analysis Fails "Pin to Pin Skew Constraint" after installing 11.4.1

DSP Tools

(Xilinx Answer 34181) 11.4.1 - System Generator for DSP - What are the known issues in using System Generator 11.4 with ISE 11.4.1?

链接问答记录

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
34181 11.4.1 - System Generator for DSP - What are the known issues in using System Generator 11.4 with ISE 11.4.1? N/A N/A
34146 Virtex-6 Integrated Block Wrapper v1.4 for PCI Express - Timing Analysis Fails "Pin to Pin Skew Constraint" after Installing 11.4.1 N/A N/A
34107 11.4 EDK - MMCM divide parameter and its effect on Clock Generator N/A N/A
34094 MIG v3.3, Virtex-6 FPGA DDR2/DDR3/QDRII+/RLDRAM - MMCM CLKFBOUT_MULT_F = 2,3,4 not valid, manual modification required N/A N/A
34159 LogiCORE IP XAUI v9.1 - The Virtex-6 FPGA Example Design MMCMs can cause DRC errors N/A N/A
34160 LogiCORE IP RXAUI v1.1 - The Virtex-6 FPGA Example Design MMCM can cause DRC errors N/A N/A
34161 LogiCORE IP 10-Gigabit Ethernet MAC v9.3 - The Virtex-6 Example Design MMCM instances can cause DRC errors N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
34196 SPI-3 Link Layer v6.1/v7.1 - "ERROR:PhysDesignRules:1997 - The computed value for the VCO operating frequency of MMCM_ADV..." N/A N/A
34195 Serial RapidIO v5.4 - "PhysDesignRules:1997 - The computed value for the VCO operating frequency of MMCM_ADV..." N/A N/A
34181 11.4.1 - System Generator for DSP - What are the known issues in using System Generator 11.4 with ISE 11.4.1? N/A N/A
34177 11.5 EDK, plbv46_pcie_v4_03_a - Virtex-6 ERROR:PhysDesignRules:1995 - The computed value for the VCO operating frequency of MMCM_ADV instance is calculated to be 500.000000 MHz N/A N/A
34161 LogiCORE IP 10-Gigabit Ethernet MAC v9.3 - The Virtex-6 Example Design MMCM instances can cause DRC errors N/A N/A
34160 LogiCORE IP RXAUI v1.1 - The Virtex-6 FPGA Example Design MMCM can cause DRC errors N/A N/A
34159 LogiCORE IP XAUI v9.1 - The Virtex-6 FPGA Example Design MMCMs can cause DRC errors N/A N/A
34146 Virtex-6 Integrated Block Wrapper v1.4 for PCI Express - Timing Analysis Fails "Pin to Pin Skew Constraint" after Installing 11.4.1 N/A N/A
34144 Virtex-6 Integrated Block Wrapper v1.4 for PCI Express - Incorrect MMCM VCO settings result in "ERROR:PhysDesignRules:1995 - The computed value for the VCO operating frequency..." N/A N/A
34143 Virtex-6 FPGA GTX Transceiver Wizard - Example MMCM causes errors N/A N/A
34107 11.4 EDK - MMCM divide parameter and its effect on Clock Generator N/A N/A
34094 MIG v3.3, Virtex-6 FPGA DDR2/DDR3/QDRII+/RLDRAM - MMCM CLKFBOUT_MULT_F = 2,3,4 not valid, manual modification required N/A N/A
34084 Serial RapidIO v5.4 - MMCM values incorrect for certain core settings in Virtex-6 devices N/A N/A
34066 SPI-4.2 v9.3 - MMCM VCO values outside of allowable range N/A N/A
34015 Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - The example design MMCM parameter values can cause Map errors or result in marginal operation N/A N/A
32929 Virtex-6 - 11.x Software Known Issues related to the Virtex-6 FPGA N/A N/A
33849 Virtex-6 FPGA MMCM - New Requirements for all MMCMs, VCO minimum frequency, and CLKFBOUT_MULT_F values N/A N/A
AR# 34019
日期 06/07/2012
状态 Archive
Type 已知问题
器件
Tools