We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34085

Design Assistant for PCI Express - Hardware Debug


This answer record identifies starting points when debugging hardware related issues to PCI Express.

NOTE: This answer record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536).TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.


The system is booting, but the endpoint is not recognized by hardware; see (Xilinx Answer 34777).

The system is hanging or locking up during the boot process or after data transfers begin; see (Xilinx Answer 35034).

the device is recognized, but problems occur during operation of the design; see (Xilinx Answer 35033).

For link training issues debugging guide (Virtex-5 Integrated PCI Express Block Plus); see (Xilinx Answer 42368).

Revision History
12/10/2011 - Added Answer Record42368
08/13/2010 - Initial Release



AR# 34085
日期 12/15/2012
状态 Active
Type 综合文章
  • Spartan-6 LXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6 HXT
  • Less
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )