AR# 34146

Virtex-6 Integrated Block Wrapper v1.4 for PCI Express - Timing Analysis Fails "Pin to Pin Skew Constraint" after Installing 11.4.1

描述

After installing ISE 11.4.1 design tools update, designs using the Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express may fail a "Pin to Pin Skew Constraint" even though the Timing Score is 0. For more information about 11.4.1, see (Xilinx Answer 34019).

解决方案

It would show up in the PAR report similar to this:

Article 34146 Figure 1
Article 34146 Figure 1


And the timing report would show:

Article 34146 Figure 2
Article 34146 Figure 2

This error can be safely ignored. It is not a legitimate failure due to incorrect skew analysis by the software. This problem is being fixed and planned to be fixed in ISE 12.1.

Revision History
01/26/2010 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34019 ISE Design Suite 11.4.1 - Known Issues for Virtex-6 FPGA Service Pack N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
34019 ISE Design Suite 11.4.1 - Known Issues for Virtex-6 FPGA Service Pack N/A N/A
AR# 34146
日期 01/21/2013
状态 Active
Type 已知问题
器件
IP