AR# 34276


Spartan-6 FPGA - Can the IODELAY2 be used to delay an output in Variable Mode?


Can the IODELAY2 be used to delay an output in Variable Mode? If not, how should an output be variably delayed?


The IODELAY2 can only be used in Variable Mode to delay inputs. When using the IODELAY2 with an output, it can only be used in FIXED delay mode.

ISE 12.1 and later simulation models properlymodel the supported functionality.Previous versions of software, ISE 11.4 and earlier,containedsimulation models which incorrectly allowed variable mode delays on outputs.

The Spartan-6 FPGA SelectIO User Guide, v1.3, states the followingwhen discussing VARIABLE_FROM_ZERO and VARIABLE_FROM_HALF_MAX modes: These modes are only available when the delay line is being used for delaying input signals.

If you need a variable ODELAY, there is a possible work-around which requires using a free I/O (or un-bonded I/O) and declaring it as a bi-directional pin. The input path of this bi-directional pin can then be set to VARIABLE delay and routed back to the desired output pin as shown in the following image:

Using this method, there is small limitation in that the route from the IDELAY to the output pad (shown in red) is local routing. This means that it is not ideal for high speed CLKs or Data signals. TheDATAOUT2 port from the IODELAY2 should be used so that the tools automatically use the ILOGIC route-thru, which is required for the input delay to access the local routing (in red) to an output pin.



Answer Number 问答标题 问题版本 已解决问题的版本
46791 Spartan-6 FPGA Design Assistant - Troubleshoot Common Fabric Problems N/A N/A
AR# 34276
日期 03/01/2013
状态 Active
Type 综合文章
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