This section of the MIG Design Assistant focuses on Core Generation for 7 series and Virtex-6 FPGA DDR3/DDR2 designs. Please select from the options belowto find information related to your specific question.
NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
Using the CORE Generator tool - (Xilinx Answer 34321)
Using Project Navigator - (Xilinx Answer 37424)
MIG Options - (Xilinx Answer 34322)
MIG Output - (Xilinx Answer 34323)
Updating a MIG core to a new MIG version - (Xilinx Answer 34386)
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 34321 | MIG 7 Series and Virtex-6 DDR2/DDR3 - Using the CORE Generator tool | N/A | N/A |
| 34323 | MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Output | N/A | N/A |
| 34386 | MIG 7 Series and Virtex-6 DDR2/DDR3 - Verify UCF and Update Design and UCF | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 34321 | MIG 7 Series and Virtex-6 DDR2/DDR3 - Using the CORE Generator tool | N/A | N/A |
| 37424 | MIG 7 Series and Virtex-6 DDR2/DDR3 - Using Project Navigator | N/A | N/A |
| 34322 | MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Options | N/A | N/A |
| 34386 | MIG 7 Series and Virtex-6 DDR2/DDR3 - Verify UCF and Update Design and UCF | N/A | N/A |
| 34318 | MIG 7 Series and Virtex-6 DDR2/DDR3 - Description of Output Directory/Files | N/A | N/A |
| 34323 | MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Output | N/A | N/A |