UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34283

MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation

描述

This section of the MIG Design Assistant focuses on Core Generation for 7 series and Virtex-6 FPGA DDR3/DDR2 designs. Please select from the options belowto find information related to your specific question.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Using the CORE Generator tool - (Xilinx Answer 34321)

Using Project Navigator - (Xilinx Answer 37424)

MIG Options - (Xilinx Answer 34322)

MIG Output - (Xilinx Answer 34323)

Updating a MIG core to a new MIG version - (Xilinx Answer 34386)

链接问答记录

主要问答记录

子答复记录

相关答复记录

AR# 34283
日期 10/04/2012
状态 Active
Type 解决方案中心
器件 More Less
IP
的页面